Lpuart Control Register (Lpuartx_Ctrl) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

This field is reserved.

This read-only field is reserved and always has the value 0.

37.3.3 LPUART Control Register (LPUARTx_CTRL)

This read/write register controls various optional features of the LPUART system. This

Address: Base address + 8h offset

Receive Bit 8 / Transmit Bit 9

R8 is the ninth data bit received when the LPUART is configured for 9-bit or 10-bit data formats. When

reading 9-bit or 10-bit data, read R8 before reading LPUART_DATA.

T9 is the tenth data bit received when the LPUART is configured for 10-bit data formats. When writing 10-

bit data, write T9 before writing LPUART_DATA. If T9 does not need to change from its previous value,

such as when it is used to generate address mark or parity, they it need not be written each time

LPUART_DATA is written.

Receive Bit 9 / Transmit Bit 8

R9 is the tenth data bit received when the LPUART is configured for 10-bit data formats. When reading

10-bit data, read R9 before reading LPUART_DATA

T8 is the ninth data bit received when the LPUART is configured for 9-bit or 10-bit data formats. When

writing 9-bit or 10-bit data, write T8 before writing LPUART_DATA. If T8 does not need to change from its

previous value, such as when it is used to generate address mark or parity, they it need not be written

each time LPUART_DATA is written.

LPUARTx_STAT field descriptions (continued)

ORIE NEIE FEIE PEIE

LPUARTx_CTRL field descriptions

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KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Freescale Semiconductor, Inc.