Data Transmission Length - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Functional description
received (the number is decided by configuration register[s] of the DMA controller) is
received or no receive DMA request is generated again because the SPI transmission is
finished.
When the FIFO feature is supported: In FIFO mode (FIFOMODE=1) and when a data
length of 8 bits is selected (SPIMODE=0), the DMA transfer for one receive DMA
request can read more than 1 byte (up to 8 bytes) from the SPI data register because the
RX FIFO can hold 8 bytes. In FIFO mode (FIFOMODE=1) and when a data length of 16
bits is selected (SPIMODE=1), the DMA transfer for one receive DMA request can read
more than 1 word (up to 4 words) from the DH:DL registers because the RX FIFO can
hold 4 words. A larger number of bytes or words transferred from the SPI data register to
memory for one receive DMA request results in a lower total number of receive DMA
requests.

35.5.6 Data Transmission Length

The SPI can support data lengths of 8 or 16 bits. The length can be configured with the
SPIMODE bit in the SPIx_C2 register.
In 8-bit mode (SPIMODE = 0), the SPI Data Register is comprised of one byte:
SPIx_DL. The SPI Match Register is also comprised of only one byte: SPIx_ML. Reads
of SPIx_DH and SPIx_MH will return zero. Writes to SPIx_DH and SPIx_MH will be
ignored.
In 16-bit mode (SPIMODE = 1), the SPI Data Register is comprised of two bytes:
SPIx_DH and SPIx_DL. Reading either byte (SPIx_DH or SPIx_DL) latches the contents
of both bytes into a buffer where they remain latched until the other byte is read. Writing
to either byte (SPIx_DH or SPIx_DL) latches the value into a buffer. When both bytes
have been written, they are transferred as a coherent 16-bit value into the transmit data
buffer.
In 16-bit mode, the SPI Match Register is also comprised of two bytes: SPIx_MH and
SPIx_ML. There is no buffer mechanism for the reading of SPIxMH and SPIxML since
they can only be changed by writing at CPU side. Writing to either byte (SPIx_MH or
SPIx_ML) latches the value into a buffer. When both bytes have been written, they are
transferred as a coherent 16-bit value into the SPI Match Register.
Any switching between 8- and 16-bit data transmission length (controlled by SPIMODE
bit) in master mode will abort a transmission in progress, force the SPI system into idle
state, and reset all status bits in the SPIx_S register. To initiate a transfer after writing to
SPIMODE, the SPIx_S register must be read with SPTEF = 1, and data must be written
to SPIx_DH:SPIx_DL in 16-bit mode (SPIMODE = 1) or SPIx_DL in 8-bit mode
(SPIMODE = 0).
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
594 Freescale Semiconductor, Inc.