Introduction; Programming Model; High-Level Device Clocking Diagram - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Chapter 5
Clock Distribution

5.1 Introduction

This chapter presents the clock architecture for the device, the overview of the clocks and
includes a terminology section.
The Cortex M0+ resides within a synchronous core platform, where the processor and
bus masters, flash memory, and peripheral clocks can be configured independently. The
clock distribution figure shows how clocks from the lite version of Multi Clock
Generation (MCG-Lite) and OSC module are distributed to the microcontroller's other
function units. Some modules in the microcontroller have selectable clock input.

5.2 Programming model

The selection and multiplexing of system clock sources is controlled and programmed via
the Clock Generation Module. The setting of clock dividers and module clock gating for
the system are programmed via the SIM module. Refer to the
sections for detailed register and bit descriptions.

5.3 High-level device clocking diagram

The following system
multiplexers, dividers, and clock gates shown in the following figure:
Multiplexers
Dividers
Clock gates
Freescale Semiconductor, Inc.
oscillator, MCG_Lite, and
OSC
MCG_Cx
—
OSC_CR
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
MCG_Lite
SIM module registers control the
MCG-Lite
MCG_Cx
MCG_Cx
MCG_C1
and SIM
SIM
SIM_SOPT1, SIM_SOPT2
SIM_CLKDIVx
SIM_SCGCx
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