Analog Reference Options - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table 2-11. Module-to-module interconnects (continued)
Peripheral Signal
PIT TIF0
PIT TIF1
Peripheral Signal
LPTMR Hardware
trigger
TPMx TOF
PIT CHx TIF0, TIF1
RTC ALARM or
SECONDS
EXTRG_IN EXTRG_IN
CMP0 CMP0_OUT

2.3.2 Analog reference options

Several analog blocks have selectable reference voltages as shown in the below table .
These options allow analog peripherals to share or have separate analog references. Care
should be taken when selecting analog references to avoid cross talk noise.
Module
16-bit SAR ADC
12-bit DAC
CMP with 6-bit DAC
Freescale Semiconductor, Inc.
— to Use Case
Peripheral
to DMA CH0 DMA HW
Trigger
to DMA CH1 DMA HW
Trigger
Table 2-12. Module-to-FlexIO interconnects
— to Use Case
Peripheral
to FlexIO Trigger input
to FlexIO Trigger input
to FlexIO Trigger input
to FlexIO Trigger input
to FlexIO Trigger input
to FlexIO Trigger input
Table 2-13. Analog reference options
Reference option
1 - VREFH or 1.2V VREF_OUT
2 - VDDA
3 - Reserved
1 - VREFH or 1.2V VREF_OUT
2 - VDDA
Vin1 - VREFH or 1.2V VREF_OUT
Vin2 - VDD
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Control
DMA MUX register option
DMA MUX register option
Control
FlexIO_TIMCTLn[TRGSEL] (4-bit
field)
FlexIO_TIMCTLn[TRGSEL] (4-bit
field)
FlexIO_TIMCTLn[TRGSEL] (4-bit
field)
FlexIO_TIMCTLn[TRGSEL] (4-bit
field)
FlexIO_TIMCTLn[TRGSEL] (4-bit
field)
FlexIO_TIMCTLn[TRGSEL] (4-bit
field)
Comment/ Reference selection
Selected by ADCx_SC2[REFSEL]
Selected by DACx_C0[DACRFS] bit
1
Selected by CMPx_DACCR[VRSEL]
1
Chapter 2 Introduction
Comment
—
—
Comment
—
—
If PIT is triggering
the FlexIO, the
FlexIO clock must be
faster than Bus
clock.
—
—
—
47