Modes Of Operation; Lptmr Signal Descriptions; Detailed Signal Descriptions - NXP Semiconductors MKL27Z128VFM4 Reference Manual

31.2.2 Modes of operation

The following table describes the operation of the LPTMR module in various modes.

31.3 LPTMR signal descriptions

Signal
LPTMR0_ALTn

31.3.1 Detailed signal descriptions

Table 31-3. LPTMR interface—detailed signal descriptions
Signal
LPTMR_ALTn
Freescale Semiconductor, Inc.
Table 31-1. Modes of operation
Modes
Run The LPTMR operates normally.
The LPTMR continues to operate normally and
Wait may be configured to exit the low-power mode
by generating an interrupt request.
The LPTMR continues to operate normally and
Stop may be configured to exit the low-power mode
by generating an interrupt request.
The LPTMR continues to operate normally and
Low-Leakage may be configured to exit the low-power mode
by generating an interrupt request.
The LPTMR operates normally in Pulse Counter
Debug mode, but counter does not increment in Time
Counter mode.
Table 31-2. LPTMR signal descriptions
I/O Description
I Pulse Counter Input pin
I/O
I Pulse Counter Input
The LPTMR can select one of the input pins to be used in Pulse Counter mode.
State meaning
Timing
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 31 Low-Power Timer (LPTMR)
Description
Description
Assertion—If configured for pulse counter mode with
active-high input, then assertion causes the CNR to
increment.
Deassertion—If configured for pulse counter mode with
active-low input, then deassertion causes the CNR to
increment.
Assertion or deassertion may occur at any time; input may
assert asynchronously to the bus clock.
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