Introduction; Features - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Introduction

When operating from an internally generated bit clock or Audio Master Clock that is
disabled in stop modes:
In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter
is disabled after completing the current transmit frame, and, if the Receiver Stop Enable
(RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive
frame. Entry into Stop mode is prevented–not acknowledged–while waiting for the
transmitter and receiver to be disabled at the end of the current frame.
40.1.4.2 Low-leakage modes
When entering low-leakage modes, the Stop Enable (TCSR[STOPE] and
RCSR[STOPE]) bits are ignored and the SAI is disabled after completing the current
transmit and receive Frames. Entry into stop mode is prevented (not acknowledged)
while waiting for the transmitter and receiver to be disabled at the end of the current
frame.
40.2 Introduction
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The I S (or I2S) module provides a synchronous audio interface (SAI) that supports full-
duplex serial interfaces with frame synchronization such as I
codec/DSP interfaces.

40.2.1 Features

Note that some of the features are not supported across all SAI instances; see the chip-
specific information in the first section of this chapter.
• Transmitter with independent bit clock and frame sync supporting 1 data line
• Receiver with independent bit clock and frame sync supporting 1 data line
• Maximum Frame Size of 2 words
• Word size of between 8-bits and 32-bits
• Word size configured separately for first word and remaining words in frame
• Asynchronous 1 × 32-bit FIFO for each transmit and receive channel
• Supports graceful restart after FIFO error
• Supports automatic restart after FIFO error without software intervention
• Supports packing of 8-bit and 16-bit data into each 32-bit FIFO word
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KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
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S, AC97, TDM, and
Freescale Semiconductor, Inc.