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Chapter 41
General-Purpose Input/Output (GPIO)
41.1 Chip-specific GPIO information
41.1.1 GPIO instantiation information
The device includes a number of pins, PTB0, PTB1, PTD6,PTD7, PTC3, and PTC4 with
high current drive capability. These pins can be used to drive LED or power MOSFET
directly. The high drive capability applies to all functions which are multiplexed on these
pins (LPUART, TPM, SPI, I2C, CLK_OUT...etc)
41.1.1.1 Pull devices and directions
The pull devices are enabled out of POR only on RESET, NMI and respective SWD
signals. Other pins can be enabled by writing to PORTx_PCRn[PE].
All the pins have controllable pull direction using the PORTx_PCRn[PS] field. All the
pins default to pullup except for SWD_CLK, when enabled.
41.1.2 GPIO accessibility in the memory map
The GPIO is multi-ported and can be accessed directly by the core with zero wait states at
base address 0xF800_0000. It can also be accessed by the core through the cross bar/
AIPS interface at 0x400F_F000 and at an aliased slot (15) at address 0x4000_F000. All
BME operations to the GPIO space can be accomplished referencing the aliased slot (15)
at address 0x4000_F000. Only some of the BME operations can be accomplished
referencing GPIO at address 0x400F_F000.
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
821
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