Sram Retention In Low Power Modes; System Register File - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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Valid address ranges for SRAM_L and SRAM_U are then defined as:

• SRAM_L = [0x2000_0000–(SRAM_size/4)] to 0x1FFF_FFFF

• SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1]

This is illustrated in the following figure.

For example, for a device containing 16 KB of SRAM, the ranges are:

• SRAM_L: 0x1FFF_F000 – 0x1FFF_FFFF

• SRAM_U: 0x2000_0000 – 0x2000_2FFF

4.3.3 SRAM retention in low power modes

The SRAM is retained down to VLLS3 mode. In VLLS1 and VLLS0, no SRAM is

4.4 System Register file

This device includes a 32-byte register file that is powered in all power modes.

Figure 4-2. SRAM blocks memory map

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

0x2000_0000 – SRAM_size/4

0x2000_0000 + SRAM_size*(3/4) - 1

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