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Memory map and register definitions
23.4.18 ADC Minus-Side General Calibration Value Register
(ADCx_CLMD)
The Minus-Side General Calibration Value (CLMx) registers contain calibration
information that is generated by the calibration function. These registers contain seven
calibration values of varying widths: CLM0[5:0], CLM1[6:0], CLM2[7:0], CLM3[8:0],
CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically set when the self-
calibration sequence is done, that is, CAL is cleared. If these registers are written by the
user after calibration, the linearity error specifications may not be met.
For more information regarding the calibration procedure, please refer to the
function
section.
Address: 4003_B000h base + 54h offset = 4003_B054h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–6
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
CLMD
Calibration Value
Calibration Value
23.4.19 ADC Minus-Side General Calibration Value Register
(ADCx_CLMS)
For more information, see CLMD register description.
Address: 4003_B000h base + 58h offset = 4003_B058h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
360
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
ADCx_CLMD field descriptions
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
Description
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
Calibration
9
8
7
6
5
4
3
2
CLMD
0
0
0
0
0
0
1
0
9
8
7
6
5
4
3
2
CLMS
0
0
0
0
1
0
0
0
Freescale Semiconductor, Inc.
1
0
1
0
1
0
0
0
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