NXP Semiconductors MKL27Z128VFM4 Reference Manual

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KL27 Sub-Family Reference Manual

Supports: MKL27Z128VFM4, MKL27Z256VFM4, MKL27Z128VFT4,

MKL27Z256VFT4, MKL27Z128VMP4, MKL27Z256VMP4,

MKL27Z128VLH4, MKL27Z256VLH4

Document Number: KL27P64M48SF6RM

Rev. 5, 01/2016

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Page 1 KL27 Sub-Family Reference Manual Supports: MKL27Z128VFM4, MKL27Z256VFM4, MKL27Z128VFT4, MKL27Z256VFT4, MKL27Z128VMP4, MKL27Z256VMP4, MKL27Z128VLH4, MKL27Z256VLH4 Document Number: KL27P64M48SF6RM Rev. 5, 01/2016...
Page 2 KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 3: Table Of Contents
Contents Section number Title Page Chapter 1 About This Document Overview..................................37 1.1.1 Purpose................................37 1.1.2 Audience................................ 37 Conventions.................................. 37 1.2.1 Numbering systems............................37 1.2.2 Typographic notation............................. 38 1.2.3 Special terms..............................38 Chapter 2 Introduction Overview..................................39 2.1.1 Sub-family introduction..........................39 Module functional categories............................40 2.2.1 ARM Cortex-M0+ core modules........................
Page 4 Section number Title Page ARM Cortex-M0+ core introduction..........................49 3.1.1 Buses, interconnects, and interfaces......................49 3.1.2 System tick timer............................49 3.1.3 Debug facilities.............................. 49 3.1.4 Core privilege levels............................50 Nested vectored interrupt controller (NVIC) .......................50 3.2.1 Interrupt priority levels..........................50 3.2.2 Non-maskable interrupt..........................50 3.2.3...
Page 5 Section number Title Page 4.7.2 Peripheral bridge (AIPS-Lite) memory map....................61 Chapter 5 Clock Distribution Introduction...................................65 Programming model..............................65 High-level device clocking diagram..........................65 Clock definitions................................66 5.4.1 Device clock summary...........................67 Internal clocking requirements............................. 69 5.5.1 Clock divider values after reset........................70 5.5.2 VLPR mode clocking.............................70 Clock gating..................................
Page 6 Section number Title Page 6.2.3 MCU resets..............................83 6.2.4 RESET pin ..............................84 Boot....................................84 6.3.1 Boot sources..............................85 6.3.2 FOPT boot options............................85 6.3.3 Boot sequence..............................87 Chapter 7 Power Management Introduction...................................89 Clocking modes................................89 7.2.1 Partial Stop..............................89 7.2.2 DMA Wakeup..............................
Page 7 Section number Title Page Debug resets..................................108 Micro Trace Buffer (MTB)............................108 Debug in low-power modes............................109 Debug and security............................... 110 Chapter 10 Pinouts and Packaging 10.1 Introduction...................................111 10.2 Signal multiplexing integration............................ 111 10.2.1 Clock gating..............................112 10.2.2 Signal multiplexing constraints........................112 10.3 KL27 Signal Multiplexing and Pin Assignments......................
Page 8 Section number Title Page 11.6 Detailed signal description............................129 11.7 Memory map and register definition..........................129 11.7.1 Pin Control Register n (PORTx_PCRn)......................135 11.7.2 Global Pin Control Low Register (PORTx_GPCLR)..................138 11.7.3 Global Pin Control High Register (PORTx_GPCHR)................... 138 11.7.4 Interrupt Status Flag Register (PORTx_ISFR)....................139 11.8 Functional description..............................139 11.8.1...
Page 9 Section number Title Page 12.3.13 Flash Configuration Register 1 (SIM_FCFG1)..................... 164 12.3.14 Flash Configuration Register 2 (SIM_FCFG2)..................... 165 12.3.15 Unique Identification Register Mid-High (SIM_UIDMH)................166 12.3.16 Unique Identification Register Mid Low (SIM_UIDML)................167 12.3.17 Unique Identification Register Low (SIM_UIDL)..................167 12.3.18 COP Control Register (SIM_COPC)......................168 12.3.19 Service COP (SIM_SRVCOP)........................169 12.4 Functional description..............................169...
Page 10 Section number Title Page 13.6 Kinetis Bootloader Status Error Codes......................... 220 13.7 Bootloader errata................................221 Chapter 14 System Mode Controller (SMC) 14.1 Chip-specific SMC information............................223 14.2 Introduction...................................223 14.3 Modes of operation............................... 223 14.4 Memory map and register descriptions.........................225 14.4.1 Power Mode Protection register (SMC_PMPROT)..................226 14.4.2 Power Mode Control register (SMC_PMCTRL)...................227 14.4.3...
Page 11 Section number Title Page 15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)............244 15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)............245 15.5.3 Regulator Status And Control register (PMC_REGSC)................246 Chapter 16 Miscellaneous Control Module (MCM) 16.1 Introduction...................................249 16.1.1...
Page 12 Section number Title Page 18.2.2 Modes of operation............................265 18.2.3 Block diagram..............................266 18.3 LLWU signal descriptions............................267 18.4 Memory map/register definition........................... 267 18.4.1 LLWU Pin Enable 1 register (LLWU_PE1)....................268 18.4.2 LLWU Pin Enable 2 register (LLWU_PE2)....................269 18.4.3 LLWU Pin Enable 3 register (LLWU_PE3)....................270 18.4.4 LLWU Pin Enable 4 register (LLWU_PE4)....................271 18.4.5...
Page 13 Section number Title Page 19.3.3 Peripheral Access Control Register (AIPS_n)....................0 19.4 Functional description..............................291 19.4.1 Access support............................... 291 Chapter 20 Direct Memory Access Multiplexer (DMAMUX) 20.1 Chip-specific DMAMUX information......................... 293 20.1.1 DMA MUX Request Sources........................293 20.1.2 DMA transfers via PIT trigger........................295 20.2 Introduction...................................295 20.2.1...
Page 14 Section number Title Page 21.3.1 Source Address Register (DMA_SARn)....................... 311 21.3.2 Destination Address Register (DMA_DARn)....................312 21.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............313 21.3.4 DMA Control Register (DMA_DCRn)......................315 21.4 Functional Description..............................319 21.4.1 Transfer requests (Cycle-Steal and Continuous modes)................319 21.4.2 Channel initialization and startup........................
Page 15 Section number Title Page 23.1.5 Alternate clock............................... 337 23.2 Introduction...................................338 23.2.1 Features................................338 23.2.2 Block diagram..............................339 23.3 ADC signal descriptions............................... 340 23.3.1 Analog Power (VDDA)..........................340 23.3.2 Analog Ground (VSSA)..........................340 23.3.3 Voltage Reference Select..........................340 23.3.4 Analog Channel Inputs (ADx)........................341 23.3.5 Differential Analog Channel Inputs (DADx)....................341 23.4...
Page 16 Section number Title Page 23.4.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS)............360 23.4.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4)............361 23.4.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM3)............361 23.4.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2)............362 23.4.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1)............
Page 17 Section number Title Page 24.1.4 CMP trigger mode............................392 24.2 Introduction...................................393 24.2.1 CMP features..............................393 24.2.2 6-bit DAC key features..........................394 24.2.3 ANMUX key features............................ 394 24.2.4 CMP, DAC and ANMUX diagram........................394 24.2.5 CMP block diagram............................395 24.3 Memory map/register definitions..........................397 24.3.1 CMP Control Register 0 (CMPx_CR0)......................
Page 18 Section number Title Page Chapter 25 12-bit Digital-to-Analog Converter (DAC) 25.1 Introduction...................................413 25.2 Features..................................413 25.3 Block diagram................................413 25.4 Memory map/register definition........................... 414 25.4.1 DAC Data Low Register (DACx_DATnL)....................415 25.4.2 DAC Data High Register (DACx_DATnH)....................415 25.4.3 DAC Status Register (DACx_SR)......................... 416 25.4.4 DAC Control Register (DACx_C0).......................
Page 19 Section number Title Page 26.3.2 Voltage Reference Enabled, SC[VREFEN] = 1.................... 428 26.4 Internal voltage regulator..............................430 26.5 Initialization/Application Information.......................... 430 Chapter 27 Multipurpose Clock Generator Lite (MCG_Lite) 27.1 Introduction ..................................433 27.1.1 Features ................................. 433 27.1.2 Block diagram ............................... 434 27.2 Memory map and register definition..........................434 27.2.1 MCG Control Register 1 (MCG_C1)......................435...
Page 20 Section number Title Page 28.6 External Crystal / Resonator Connections........................445 28.7 External Clock Connections............................447 28.8 Memory Map/Register Definitions..........................447 28.8.1 OSC Memory Map/Register Definition......................448 28.9 Functional Description..............................449 28.9.1 OSC module states............................449 28.9.2 OSC module modes............................451 28.9.3 Counter................................453 28.9.4...
Page 21 Section number Title Page 29.4.1 Status and Control (TPMx_SC)........................463 29.4.2 Counter (TPMx_CNT)........................... 464 29.4.3 Modulo (TPMx_MOD)..........................465 29.4.4 Channel (n) Status and Control (TPMx_CnSC).....................466 29.4.5 Channel (n) Value (TPMx_CnV)........................468 29.4.6 Capture and Compare Status (TPMx_STATUS)................... 468 29.4.7 Channel Polarity (TPMx_POL)........................470 29.4.8 Configuration (TPMx_CONF)........................
Page 22 Section number Title Page 30.2.1 Block diagram..............................488 30.2.2 Features................................488 30.3 Signal description................................489 30.4 Memory map/register description..........................489 30.4.1 PIT Module Control Register (PIT_MCR)....................490 30.4.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)................. 491 30.4.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)................. 491 30.4.4 Timer Load Value Register (PIT_LDVALn)....................492 30.4.5...
Page 23 Section number Title Page 31.4 Memory map and register definition..........................504 31.4.1 Low Power Timer Control Status Register (LPTMRx_CSR)................504 31.4.2 Low Power Timer Prescale Register (LPTMRx_PSR)..................505 31.4.3 Low Power Timer Compare Register (LPTMRx_CMR)................507 31.4.4 Low Power Timer Counter Register (LPTMRx_CNR)................. 507 31.5 Functional description..............................508 31.5.1...
Page 24 Section number Title Page 32.3.7 RTC Lock Register (RTC_LR)........................521 32.3.8 RTC Interrupt Enable Register (RTC_IER)....................522 32.4 Functional description..............................523 32.4.1 Power, clocking, and reset..........................523 32.4.2 Time counter..............................524 32.4.3 Compensation..............................524 32.4.4 Time alarm..............................525 32.4.5 Update mode..............................525 32.4.6 Register lock..............................526 32.4.7 Interrupt................................526 Chapter 33...
Page 25 Section number Title Page 33.4.5 USB transaction............................. 539 33.5 Memory map/Register definitions..........................541 33.5.1 Peripheral ID register (USBx_PERID)......................543 33.5.2 Peripheral ID Complement register (USBx_IDCOMP).................543 33.5.3 Peripheral Revision register (USBx_REV)....................544 33.5.4 Peripheral Additional Info register (USBx_ADDINFO)................544 33.5.5 Interrupt Status register (USBx_ISTAT)....................... 545 33.5.6 Interrupt Enable register (USBx_INTEN).....................
Page 26 Section number Title Page Chapter 34 USB Voltage Regulator (VREG) 34.1 Introduction...................................563 34.1.1 Overview................................ 563 34.1.2 Features................................564 34.1.3 Modes of Operation............................565 34.2 USB Voltage Regulator Module Signal Descriptions....................565 Chapter 35 Serial Peripheral Interface (SPI) 35.1 Chip-specific SPI information............................567 35.2 Introduction...................................567 35.2.1...
Page 27 Section number Title Page 35.4.10 SPI control register 3 (SPIx_C3)........................586 35.5 Functional description..............................588 35.5.1 General................................588 35.5.2 Master mode..............................588 35.5.3 Slave mode..............................590 35.5.4 SPI FIFO Mode.............................. 591 35.5.5 SPI Transmission by DMA..........................592 35.5.6 Data Transmission Length..........................594 35.5.7 SPI clock formats............................
Page 28 Section number Title Page 36.4.2 I2C Frequency Divider register (I2Cx_F)...................... 615 36.4.3 I2C Control Register 1 (I2Cx_C1)......................... 616 36.4.4 I2C Status register (I2Cx_S).......................... 618 36.4.5 I2C Data I/O register (I2Cx_D)........................620 36.4.6 I2C Control Register 2 (I2Cx_C2)......................... 620 36.4.7 I2C Programmable Input Glitch Filter Register (I2Cx_FLT)................ 621 36.4.8 I2C Range Address register (I2Cx_RA)......................
Page 29 Section number Title Page 37.2.1 Features................................647 37.2.2 Modes of operation............................648 37.2.3 Signal Descriptions............................649 37.2.4 Block diagram..............................649 37.3 Register definition.................................651 37.3.1 LPUART Baud Rate Register (LPUARTx_BAUD)..................652 37.3.2 LPUART Status Register (LPUARTx_STAT)....................654 37.3.3 LPUART Control Register (LPUARTx_CTRL)................... 658 37.3.4 LPUART Data Register (LPUARTx_DATA)....................
Page 30 Section number Title Page 38.4.4 UART Control Register 2 (UARTx_C2)....................... 685 38.4.5 UART Status Register 1 (UARTx_S1)......................687 38.4.6 UART Status Register 2 (UARTx_S2)......................689 38.4.7 UART Control Register 3 (UARTx_C3)....................... 691 38.4.8 UART Data Register (UARTx_D).........................692 38.4.9 UART Match Address Registers 1 (UARTx_MA1)..................693 38.4.10 UART Match Address Registers 2 (UARTx_MA2)..................694 38.4.11 UART Control Register 4 (UARTx_C4).......................
Page 31 Section number Title Page 38.5.4 Data format (non ISO-7816).......................... 726 38.5.5 Single-wire operation............................. 729 38.5.6 Loop operation............................... 729 38.5.7 ISO-7816/smartcard support.......................... 730 38.6 Reset....................................735 38.7 System level interrupt sources............................735 38.7.1 RXEDGIF description............................736 38.8 DMA operation................................737 38.9 Application information..............................738 38.9.1 ISO-7816 initialization sequence........................
Page 32 Section number Title Page 39.3.2 Parameter Register (FLEXIO_PARAM)....................... 751 39.3.3 FlexIO Control Register (FLEXIO_CTRL)....................752 39.3.4 Shifter Status Register (FLEXIO_SHIFTSTAT)...................753 39.3.5 Shifter Error Register (FLEXIO_SHIFTERR)....................754 39.3.6 Timer Status Register (FLEXIO_TIMSTAT)....................754 39.3.7 Shifter Status Interrupt Enable (FLEXIO_SHIFTSIEN)................755 39.3.8 Shifter Error Interrupt Enable (FLEXIO_SHIFTEIEN)................756 39.3.9 Timer Interrupt Enable Register (FLEXIO_TIMIEN)...................756 39.3.10 Shifter Status DMA Enable (FLEXIO_SHIFTSDEN)..................
Page 33 Section number Title Page 39.5.7 I2S Slave................................ 782 Chapter 40 Synchronous Audio Interface (SAI) 40.1 Chip-specific I2S information............................785 40.1.1 Instantiation information..........................785 40.1.2 I2S Interrupts..............................785 40.1.3 I2S/SAI clocking............................785 40.1.4 I2S/SAI operation in low power modes......................787 40.2 Introduction...................................788 40.2.1 Features................................788 40.2.2 Block diagram..............................
Page 34 Section number Title Page 40.5 Functional description..............................812 40.5.1 SAI clocking..............................812 40.5.2 SAI resets............................... 814 40.5.3 Synchronous modes............................815 40.5.4 Frame sync configuration..........................815 40.5.5 Data FIFO..............................816 40.5.6 Word mask register............................819 40.5.7 Interrupts and DMA requests......................... 819 Chapter 41 General-Purpose Input/Output (GPIO) 41.1 Chip-specific GPIO information...........................821...
Page 35 Section number Title Page 42.1 Introduction...................................831 42.1.1 Overview................................ 832 42.1.2 Features................................832 42.1.3 Modes of operation............................833 42.2 Memory map and register definition..........................833 42.3 Functional description..............................833 42.3.1 BME decorated stores............................ 834 42.3.2 BME decorated loads............................. 841 42.3.3 Additional details on decorated addresses and GPIO accesses..............847 42.4 Application information..............................848 Chapter 43...
Page 36 Section number Title Page 44.5 Functional description..............................884 Chapter 45 Flash Memory Module (FTFA) 45.1 Introduction...................................887 45.1.1 Features................................887 45.1.2 Block Diagram............................... 888 45.1.3 Glossary................................. 889 45.2 External Signal Description............................890 45.3 Memory Map and Registers............................890 45.3.1 Flash Configuration Field Description......................891 45.3.2 Program Flash IFR Map..........................891 45.3.3...
Page 37: About This Document
Chapter 1 About This Document 1.1 Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the Freescale KL27 microcontroller. 1.1.2 Audience A reference manual is primarily for system architects and software application developers who are using or considering using a Freescale product in a system. 1.2 Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems:...
Page 38: Typographic Notation
Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers.
Page 39: Introduction
Chapter 2 Introduction 2.1 Overview ® ® Information found here provides an overview of the Kinetis L series of ARM Cortex M0+ MCUs and KL27 product family. It also presents high-level descriptions of the modules available on the devices covered by this document. 2.1.1 Sub-family introduction The device is highly-integrated, market leading ultra low-power 32-bit microcontroller based on the enhanced Cortex-M0+ (CM0+) core platform.
Page 40: Module Functional Categories
Module functional categories 2.2 Module functional categories The modules on this device are grouped into functional categories. Information found here describes the modules assigned to each category in more detail. Table 2-1. Module functional categories Module category Description ® ARM Cortex-M0+ core •...
Page 41: Arm Cortex-M0+ Core Modules
Chapter 2 Introduction 2.2.1 ARM Cortex-M0+ core modules The following core modules are available on this device. Table 2-2. Core modules Module Description ARM Cortex-M0+ The ARM Cortex-M0+ is the newest member of the Cortex M Series of processors targeting microcontroller applications focused on very cost sensitive, deterministic, interrupt driven environments.
Page 42: Memories And Memory Interfaces
Module functional categories Table 2-3. System modules (continued) Module Description Miscellaneous control module (MCM) The MCM includes integration logic and details. Crossbar switch lite (AXBS-Lite) The AXBS connects bus masters and bus slaves, allowing all bus masters to access different bus slaves simultaneously and providing arbitration among the bus masters when they access the same slave.
Page 43: Security And Integrity Modules
Chapter 2 Introduction 2.2.5 Security and integrity modules The following security and integrity modules are available on this device: Table 2-6. Security and integrity modules Module Description Watchdog timer (WDOG) Watchdog timer keeps a watch on the system functioning and resets it in case of its failure.
Page 44: Communication Interfaces
Module functional categories Table 2-8. Timer modules (continued) Module Description • Support the generation of an interrupt and/or DMA request per channel • Support the generation of an interrupt and/or DMA request when the counter overflows • Support selectable trigger input to optionally reset or cause the counter to start incrementing.
Page 45: Human-Machine Interfaces
Chapter 2 Introduction 2.2.9 Human-machine interfaces The following human-machine interfaces (HMI) are available on this device: Table 2-10. HMI modules Module Description General purpose input/output (GPIO) Some general purpose input or output (GPIO) pins are capable of interrupt and DMA request generation. 2.3 Module to module interconnects 2.3.1 Interconnection overview The following table lists the module to module interconnections for this device.
Page 46 Module to module interconnects Table 2-11. Module-to-module interconnects (continued) Peripheral Signal — Use Case Control Comment Peripheral EXTRG_IN EXTRG_IN SIM_SOPT7[ADC0TRGSEL], — (Trigger) Triggering (A SIM_SOPT7[ADC0PRETRGSEL] or B) to select A or B CMP0 CMP0_OUT SIM_SOPT7[ADC0TRGSEL], — (Trigger) Triggering (A SIM_SOPT7[ADC0PRETRGSEL] or B) to select A or B CMP0...
Page 47: Analog Reference Options
Chapter 2 Introduction Table 2-11. Module-to-module interconnects (continued) Peripheral Signal — Use Case Control Comment Peripheral TIF0 DMA CH0 DMA HW DMA MUX register option — Trigger TIF1 DMA CH1 DMA HW DMA MUX register option — Trigger Table 2-12. Module-to-FlexIO interconnects Peripheral Signal —...
Page 48 Module to module interconnects 1. Use this option for the best ADC operation. NOTE VREFH pin can be used as filter capacitor pin for high precision 1.2V VREF_OUT. When 1.2V VREF is enabled, VREFH is 1.2V VREF_OUT. Also, when 1.2V VREF module is enabled, adding supply to VREFH pad, which is a dedicated 1.2 VREF_OUT pad, from external is prohibited.
Page 49: Core Overview
Chapter 3 Core Overview 3.1 ARM Cortex-M0+ core introduction The enhanced ARM Cortex M0+ is the member of the Cortex-M Series of processors targeting microcontroller cores focused on very cost sensitive, low power applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It also has hardware debug functionality including support for simple program trace capability.
Page 50: Core Privilege Levels
Nested vectored interrupt controller (NVIC) 3.1.4 Core privilege levels The core on this device is implemented with both privileged and unprivileged levels. The ARM documentation uses different terms than this document to distinguish between privilege levels. If you see this term... it also means this term...
Page 51 Chapter 3 Core Overview NOTE The NVIC wake-up sources in the following table support only down to VLPS. Table 3-2. Interrupt vector assignments Address Vector NVIC Source module Source description register number ARM core system handler vectors 0x0000_0000 — — ARM core Initial stack pointer 0x0000_0004...
Page 52 Nested vectored interrupt controller (NVIC) Table 3-2. Interrupt vector assignments (continued) Address Vector NVIC Source module Source description register number 0x0000_007C ADC0 Conversion complete 0x0000_0080 CMP0 Rising or falling edge of comparator output 0x0000_0084 TPM0 Overflow or channel interrupt 0x0000_0088 TPM1 Overflow or channel interrupt 0x0000_008C...
Page 53: Awic Introduction
Chapter 3 Core Overview • NVICIPR2 • To determine the particular IRQ's field location within these particular registers: • NVICIPR2 field starting location = 8 * (IRQ mod 4) + 6 = 22 Since the NVICIPR fields are 2-bit wide (4 priority levels), the NVICIPR2 field range is 22–23.
Page 54 AWIC introduction KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 55: Memory Map
Flash Memory (KB) Block 0 (P-Flash) address Block 1 (P-Flash) address range range MKL27Z128VMP4, 0x0000_0000 – 0x0000_FFFF 0x0001_0000 – 0x0001_FFFF MKL27Z128VLH4, MKL27Z128VFM4, MKL27Z128VFT4 MKL27Z256VMP4, 0x0000_0000 – 0x0001_FFFF 0x0002_0000 – 0x0003_FFFF MKL27Z256VLH4, MKL27Z256VFM4, MKL27Z256VFT4 KL27 Sub-Family Reference Manual , Rev. 5, 01/2016...
Page 56: Flash Security
Flash memory 4.2.1 Flash memory map The flash memory and the flash registers are located at different base addresses as shown in the figure found here. The base address for each is specified in System memory map. Flash memory base address Registers Flash base address Flash configuration field...
Page 57: Ftfa_Fopt Register
This device contains SRAM which could be accessed by bus masters through the cross- bar switch. The amount of SRAM for the devices covered in this document is shown in the following table. Table 4-2. KL27 SRAM memory size Device SRAM MKL27Z128VFM4 32 KB MKL27Z256VFM4 32 KB MKL27Z128VFT4 32 KB...
Page 58: Sram Retention In Low Power Modes
System Register file Valid address ranges for SRAM_L and SRAM_U are then defined as: • SRAM_L = [0x2000_0000–(SRAM_size/4)] to 0x1FFF_FFFF • SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1] This is illustrated in the following figure. 0x2000_0000 – SRAM_size/4 SRAM_L 0x1FFF_FFFF 0x2000_0000 SRAM_U 0x2000_0000 + SRAM_size*(3/4) - 1 Figure 4-2.
Page 59: System Memory Map
Chapter 4 Memory Map Also, it retains contents during low-voltage detect (LVD) events and is only reset during a power-on reset. 4.5 System memory map The table found here shows the high-level device memory map. Table 4-3. System memory map System 32-bit address range Destination slave Access...
Page 60: Bit Manipulation Engine
Bit Manipulation Engine 4.6 Bit Manipulation Engine The Bit Manipulation Engine (BME) provides hardware support for atomic read-modify- write memory operations to the peripheral address space. By combining the basic load and store instruction support in the Cortex-M instruction set architecture with the concept of decorated storage provided by the BME, the resulting implementation provides a robust and efficient read-modify-write capability to this class of ultra low-end microcontrollers.
Page 61: Read-After-Write Sequence And Required Serialization Of Memory Operations
Chapter 4 Memory Map 4.7.1 Read-after-write sequence and required serialization of memory operations In some situations, a write to a peripheral must be completed fully before a subsequent action can occur. Examples of such situations include: • Exiting an interrupt service routine (ISR) •...
Page 62 Peripheral bridge (AIPS-Lite) memory map Table 4-4. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4001_5000 — 0x4001_6000 — 0x4001_7000 — 0x4001_8000 — 0x4001_9000 — 0x4001_A000 — 0x4001_B000 — 0x4001_C000 — 0x4001_D000 — 0x4001_E000 — 0x4001_F000 —...
Page 63 Chapter 4 Memory Map Table 4-4. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4003_C000 — 0x4003_D000 Real Time Clock (RTC) 0x4003_E000 — 0x4003_F000 DAC0 0x4004_0000 Low-power timer (LPTMR) 0x4004_1000 System register file 0x4004_2000 — 0x4004_3000 —...
Page 64 Peripheral bridge (AIPS-Lite) memory map Table 4-4. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4006_3000 — 0x4006_4000 Multi-purpose clock Generator Lite (MCG_Lite) 0x4006_5000 System oscillator (OSC) 0x4006_6000 0x4006_7000 0x4006_8000 — 0x4006_9000 — 0x4006_A000 — 0x4006_B000 —...
Page 65: Introduction
Chapter 5 Clock Distribution 5.1 Introduction This chapter presents the clock architecture for the device, the overview of the clocks and includes a terminology section. The Cortex M0+ resides within a synchronous core platform, where the processor and bus masters, flash memory, and peripheral clocks can be configured independently. The clock distribution figure shows how clocks from the lite version of Multi Clock Generation (MCG-Lite) and OSC module are distributed to the microcontroller’s other function units.
Page 66: Clock Definitions
Clock definitions MCG_Lite CLKGEN IRC_TRIMs MCGPCLK IRC48M Clock options for some peripherals MCGIRCLK (see note) USB_EN LIRC_DIV2 IRC8M 8MHz 8MHz/ MCGOUTCLK FCRDIV Core/Platform/System clock OUTDIV1 2MHz 2MHz IRCS CLKS Bus/Flash clock OUTDIV4 System oscillator EXTAL0 OSCCLK XTAL_CLK OSCERCLK OSC32KCLK XTAL0 logic ERCLK32K Clock options for...
Page 67: Device Clock Summary
Chapter 5 Clock Distribution Clock name Description Bus clock System clock divided by OUTDIV4. Clocks the bus slaves and peripherals. Flash clock Flash memory clock On this device, it is the same as Bus clock. MCGOUTCLK MCG_Lite output of either IRC48M, IRC8M, MCG_Lite's external reference clock that sources the core, system, bus, and flash clock.
Page 68 Clock definitions Table 5-1. Clock summary (continued) Clock name Run mode VLPR mode Clock source Clock is disabled when… clock frequency clock frequency STOP2 mode, and Compute Operation SWD Clock Up to 24 MHz Up to 1 MHz SWD_CLK pin In all stop modes Flash clock Up to 24 MHz...
Page 69: Internal Clocking Requirements
Chapter 5 Clock Distribution Table 5-1. Clock summary (continued) Clock name Run mode VLPR mode Clock source Clock is disabled when… clock frequency clock frequency LPUART1 clock Up to 48 MHz Up to 8 MHz MCGIRCLK, SIM_SOPT2[LPUART1 SRC]=00 selected clock MCGPCLK, source disabled OSCERCLK...
Page 70: Clock Divider Values After Reset
Internal clocking requirements Clock Max. Frequency MCGIRCLK 8 MHz MCGPCLK 48 MHz 5.5.1 Clock divider values after reset Each clock divider is programmed via the CLKDIV1 registers of the SIM module. Two bits in the flash memory's FTFA_FOPT register control the reset value of the core clock, system clock, bus clock, and flash clock dividers as shown in the table given below: FTFA_FOPT [4,0] Core/system clock...
Page 71: Clock Gating
Chapter 5 Clock Distribution 5.6 Clock gating The clock to each module can be individually gated on and off using bits of the SCGCx registers of the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing a module, set the corresponding bit in the SCGCx register to enable the clock.
Page 72: Pmc 1-Khz Lpo Clock
Module clocks Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks Bus clock OSCERCLK — Bus clock — — Bus clock — — Internal Voltage Reference Bus clock — — (VREF) Timers Bus clock TPM clock TPM_CLKIN0, TPM_CLKIN1 Bus clock —...
Page 73: Rtc Clocking
Chapter 5 Clock Distribution MCGIRCLK COP clock OSCERCLK Bus clock SIM_COPC[COPCLKSEL] Figure 5-2. COP clock generation 5.7.3 RTC clocking The RTC module can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the RTC is to continue operating in all required low-power modes.
Page 74: Lptmr Clocking
Module clocks SIM_SOPT1[OSC32KOUT] on the selected RTC_CLKOUT pins in all modes of operation (including LLS/VLLS and System Reset), overriding the existing pin mux configuration for that pin. SIM_SOPT1[OSC32KSEL] SIM_SOPT1[OSC32KOUT] OSC32KCLK PTE0/CLKOUT32K interface ERCLK32K Other modules RTC_CLKIN] PTE26/CLKOUT32K interface Other modules OSCERCLK RTC_CLKOUT RTC 1Hz clock...
Page 75: Tpm Clocking
Chapter 5 Clock Distribution MCGIRCLK LPTMRx prescaler/glitch ERCLK32K filter clock RTC_CLKIN OSCERCLK OSC32KCLK SIM_SOPT1[OSC32KSEL] LPTMRx_PSR[PCS] Figure 5-5. LPTMRx prescaler/glitch filter clock generation 5.7.6 TPM clocking The counter for the TPM modules has a selectable clock as shown in the following figure. NOTE The chosen clock must remain enabled if the TPMx is to continue operating in all required low-power modes.
Page 76: Lpuart Clocking
Module clocks NOTE For the USB FS controller to operate, the minimum system clock frequency is 20 MHz. The USB controller also requires a 48 MHz clock. The clock source options are shown below. USB_CLKIN USB 48MHz MCGPCLK SIM_SOPT2[USBSRC] Figure 5-7. USB 48 MHz clock source 5.7.8 LPUART clocking The LPUART0 and LPUART1 have a selectable clock as shown in the following figure.
Page 77: Flexio Clocking
Chapter 5 Clock Distribution MCGIRCLK OSCERCLK LPUART0 clock MCGPCLK SIM_SOPT2[LPUART0SRC] MCGIRCLK OSCERCLK LPUART1 clock MCGPCLK SIM_SOPT2[LPUART1SRC] Figure 5-8. LPUART0 and LPUART1 clock generation 5.7.9 FlexIO clocking The FlexIO module has a selectable clock as shown in the following figure. NOTE The chosen clock must remain enabled if the FlexIO is to continue operating in all required low-power modes.
Page 78: I2S/Sai Clocking
Module clocks 5.7.10 I S/SAI clocking The audio master clock (MCLK) is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. The audio master clock can also be output to or input from a pin. The transmitter and receiver have the same audio master clock inputs.
Page 79: Reset And Boot
Chapter 6 Reset and Boot 6.1 Introduction The reset sources supported in this MCU are listed in the table found here. Table 6-1. Reset sources Reset sources Description POR reset • Power-on reset (POR) System resets • External pin reset (PIN) •...
Page 80: Power-On Reset (Por)
Reset 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (V ), the POR circuit causes a POR reset condition. As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above the LVD low threshold (V ).
Page 81 Chapter 6 Reset and Boot 6.2.2.1.1 RESET pin filter The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus clock. RCM_RPFC[RSTFLTSS], RCM_RPFC[RSTFLTSRW], and RCM_RPFW[RSTFLTSEL] control this functionality; see the chapter. The filters are asynchronously reset by Chip POR. The reset value for each filter assumes the RESET pin is negated.
Page 82 Reset 6.2.2.4 Low leakage wakeup (LLWU) The LLWU module provides the means for a number of external pins to wake the MCU from low leakage power modes. The LLWU module is functional only in low leakage power modes. In VLLSx modes, all enabled inputs to the LLWU can generate a system reset.
Page 83: Mcu Resets
Chapter 6 Reset and Boot 6.2.2.8 MDM-AP system reset request Set the System Reset Request field in the MDM-AP control register to initiate a system reset. This is the primary method for resets via the SWD interface. The system reset is held until this field is cleared.
Page 84: Reset Pin
Boot 6.2.3.4 Chip Reset not VLLS The Chip Reset not VLLS reset asserts on all reset sources except a VLLS Wakeup that does not occur via the RESET pin. It resets parts of the SMC, LLWU, and other modules that remain powered during VLLS mode. The Chip Reset not VLLS reset also causes the Chip Reset (including Early Chip Reset) to occur.
Page 85: Boot Sources
Chapter 6 Reset and Boot Some configuration information such as clock trim values stored in factory programmed flash locations is autoloaded. 6.3.1 Boot sources The CM0+ core adds support for a programmable Vector Table Offset Register (VTOR) to relocate the exception vector table. This device supports booting from: •...
Page 86 Boot The MCU uses FTFA_FOPT to configure the device at reset as shown in the following table. An FTFA_FOPT value of 0x00 is invalid and will be ignored. The FOPT register is written to 0xFF if the contents of the Flash nonvolatile option are 0x00. Table 6-2.
Page 87: Boot Sequence
Chapter 6 Reset and Boot Table 6-2. Flash Option Register (FTFA_FOPT) definition (continued) Field Value Definition Core and system clock divider (OUTDIV1) is 0x7 (divide by 8). Device is configured for VLPR mode on exit from reset. Core and system clock divider (OUTDIV1) is 0x3 (divide by 4). Device is configured for VLPR mode on exit from reset.
Page 88 Boot and FTFA_FOPT[NMI_DIS] and FTFA_FOPT[BOOTSRC_SEL] and FTFA_FOPT[BOOTPIN_OPT] as well as RCM_FM[FORCEROM] and RCM_MR[BOOTROM](See Table 6-2 and RCM block guide) : • If the NMI/BOOTCFG0 input is high or the NMI function is disabled in FTFA_FOPT, the CPU begins execution at the PC location. •...
Page 89: Power Management
Chapter 7 Power Management 7.1 Introduction Information about the various chip power modes and functionality of the individual modules in these modes can be found here. AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on power management techniques. 7.2 Clocking modes Information found here describes the various clocking modes supported on this device.
Page 90: Dma Wakeup
Clocking modes When configured for PSTOP1, both the system clock and bus clock are gated. All bus masters and bus slaves enter Stop mode, but the clock generators in the MCG and the on- chip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can be initiated by a reset or an asynchronous interrupt from a bus master or bus slave.
Page 91: Compute Operation
Chapter 7 Power Management NOTE If the requested DMA transfer cannot cause the DMA request to negate then the device will remain in a higher power state until the low power mode is fully exited. An enabled DMA wake-up can cause an aborted entry into the low power mode, if the DMA request asserts during the stop mode entry sequence (or reentry if the request asserts during a DMA wakeup) and can cause the SMC to assert its Stop Abort flag.
Page 92: Peripheral Doze
Clocking modes During Compute Operation, the AIPS peripheral space is disabled and attempted accesses generate bus errors. The private peripheral space remains accessible during Compute Operation, including the MCM, NVIC, IOPORT, and SysTick. Although access to the GPIO registers via the IOPORT is supported, the GPIO Port Data Input registers do not return valid data since clocks are disabled to the Port Control and Interrupt modules.
Page 93: Clock Gating
Chapter 7 Power Management Peripheral Doze can therefore be used to disable selected bus masters or slaves for the duration of WAIT or VLPW mode. It can also be used to disable selected bus slaves immediately on entry into any stop mode (or Compute Operation), instead of waiting for the bus masters to acknowledge the entry as part of the stop entry sequence.
Page 94 Power modes The three primary modes of operation are Run, Wait, and Stop. The WFI instruction invokes both Wait and Stop modes for the chip. The primary modes are augmented in a number of ways to provide lower power based on application needs. Table 7-1.
Page 95: Entering And Exiting Power Modes
Chapter 7 Power Management Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery •...
Page 96: Module Operation In Low-Power Modes
Module operation in low-power modes 7.5 Module operation in low-power modes The table found here illustrates the functionality of each module while the chip is in each of the low power modes. The standard behavior is shown with some exceptions for Compute Operation (CPO) and Partial Stop2 (PSTOP2).
Page 97 Chapter 7 Power Management Table 7-2. Module operation in low power modes (continued) Modules VLPR VLPW Stop VLPS VLLSx COP watchdog Optional work Optional work static with clock with clock static in CPO source enabled source enabled in stop mode in stop mode FF in PSTOP2 Clocks...
Page 98 Module operation in low-power modes Table 7-2. Module operation in low power modes (continued) Modules VLPR VLPW Stop VLPS VLLSx UART2 62.5 kbit/s 62.5 kbit/s static, wakeup static, wakeup static on edge on edge static, wakeup on edge in CPO FF in PSTOP2 SPI0 (without master mode...
Page 99 Chapter 7 Power Management Table 7-2. Module operation in low power modes (continued) Modules VLPR VLPW Stop VLPS VLLSx ADC internal clock only in HS or LS HS or LS LS compare LS compare in compare compare VLLS1/3, OFF in HS or LS VLLS0 compare in CPO...
Page 100 Module operation in low-power modes KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 101: Security
Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.1.1 Flash security The flash module provides security information to the MCU based on the state held by FTFA_FSEC[SEC].
Page 102 Introduction 8.1.2.1 Security interactions with Debug When flash security is active, the SWD port cannot access the memory resources of the MCU. Although most debug functions are disabled, the debugger can write to the Flash Mass Erase in Progress field of the MDM-AP Control register to trigger a mass erase (Erase All Blocks) command.
Page 103: Debug
Chapter 9 Debug 9.1 Introduction ™ This debug of this device is based on the ARM CoreSight architecture and is configured to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. It provides register and memory accessibility from the external debugger interface, basic run/halt control plus 2 breakpoints and 2 watchpoints.
Page 104: Swd Status And Control Registers
SWD status and control registers 9.3 SWD status and control registers Through the ARM Debug Access Port (DAP), the debugger has access to the status and control elements, implemented as registers on the DAP bus as shown in the figure found here.
Page 105: Mdm-Ap Control Register
Chapter 9 Debug DPACC APACC Data[31:0] A[3:2] RnW Data[31:0] A[3:2] RnW SW-DP See the ARM Debug Interface v5p1 Supplement. Generic Debug Port (DP) APSEL Data[31:0] A[7:4] A[3:2] RnW Decode SELECT[31:24] (APSEL) selects the AP SELECT[7:4] (APBANKSEL) selects the bank A[3:2] from the APACC selects the register within the bank AHB-AP SELECT[31:24] = 0x00 selects the AHB-AP...
Page 106: Mdm-Ap Status Register
SWD status and control registers Table 9-3. MDM-AP Control register assignments (continued) Name Secure Description If the core is in a Stop or Wait mode, this bit can be used to wake the core and transition to a halted state. System Reset Request Set to force a system reset.
Page 107 Chapter 9 Debug 9.3.2 MDM-AP Status Register Table 9-4. MDM-AP Status register assignments Name Description Flash Mass Erase Acknowledge The Flash Mass Erase Acknowledge bit is cleared after any system reset. The bit is also cleared at launch of a mass erase command due to write of Flash Mass Erase in Progress bit in MDM AP Control Register.
Page 108: Debug Resets
Debug resets Table 9-4. MDM-AP Status register assignments (continued) Name Description This bit is set during the LLS recovery sequence. The LLS Mode Exit bit is held until the debugger has had a chance to recognize that LLS was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register.
Page 109: Debug In Low-Power Modes
Chapter 9 Debug When enabled, the MTB records changes in program flow reported by the Cortex-M0+ processor, via the execution trace interface, into a configurable region of the SRAM. Subsequently, an off-chip debugger may extract the trace information, which would allow reconstruction of an instruction flow trace.
Page 110: Debug And Security
Debug and security In VLLS mode, all debug modules are powered off and reset at wakeup. In LLS mode, the debug modules retain their state but no debug activity is possible. Going into a VLLSx mode causes all the debug controls and settings to be reset. To give time to the debugger to sync up with the HW, the MDM-AP Control register can be configured to hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation.
Page 111: Pinouts And Packaging
Chapter 10 Pinouts and Packaging 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. Information found here illustrates which of this device's signals are multiplexed on which external pin. Port Control block controls which signal is present on the external pin. Refer to that chapter to find which register controls the operation of a specific pin.
Page 112: Clock Gating
KL27 Signal Multiplexing and Pin Assignments Table 10-1. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Register access Peripheral bus Peripheral bridge controller 10.2.1 Clock gating The clock to the port control module can be gated on and off using the SCGC5[PORTx] bits in the SIM module.
Page 113 Chapter 10 Pinouts and Packaging Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP — — — PTE20 ADC0_DP0/ ADC0_DP0/ PTE20 TPM1_CH0 LPUART0_ FXIO0_D4 ADC0_SE0 ADC0_SE0 — PTE21 ADC0_DM0/ ADC0_DM0/ PTE21 TPM1_CH1 LPUART0_ FXIO0_D5 ADC0_SE4a ADC0_SE4a — —...
Page 114 KL27 Signal Multiplexing and Pin Assignments Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP — PTE0 DISABLED PTE0/ SPI1_MISO LPUART1_ RTC_ CMP0_OUT I2C1_SDA CLKOUT32K CLKOUT USB0_DP USB0_DP USB0_DP USB0_DM USB0_DM USB0_DM VOUT33 VOUT33 VOUT33 VREGIN VREGIN VREGIN VDDA VDDA...
Page 115: Kl27 Family Pinouts
Chapter 10 Pinouts and Packaging Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5 FXIO0_D5 PTD6/ ADC0_SE7b ADC0_SE7b PTD6/ SPI1_MOSI LPUART0_ SPI1_MISO FXIO0_D6 LLWU_P15 LLWU_P15 PTD7 DISABLED PTD7 SPI1_MISO LPUART0_ SPI1_MOSI FXIO0_D7 10.4 KL27 Family Pinouts...
Page 116 KL27 Family Pinouts PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN USB0_DP PTC0 USB0_DM VOUT33 PTB17 VREGIN PTB16 PTE20 PTB3 PTE21 PTB2 VDDA PTB1 VREFH PTB0/LLWU_P5 VREFL PTA20 VSSA PTA19 Figure 10-3. 48 QFN Pinout diagram Figure below shows the 64 LQFP pinouts: KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 117 Chapter 10 Pinouts and Packaging PTE0 PTE1 PTC3/LLWU_P7 PTC2 USB0_DP PTC1/LLWU_P6/RTC_CLKIN USB0_DM PTC0 VOUT33 PTB19 VREGIN PTB18 PTE20 PTB17 PTE21 PTB16 PTE22 PTB3 PTE23 PTB2 VDDA PTB1 VREFH PTB0/LLWU_P5 VREFL PTA20 VSSA PTA19 Figure 10-4. 64 LQFP Pinout diagram Figure below shows the 64 MAPBGA pinouts: KL27 Sub-Family Reference Manual , Rev.
Page 118: Module Signal Description Tables
Module Signal Description Tables PTC5/ PTD4/ PTC6/ PTE0 PTD7 PTD1 PTC11 PTC8 LLWU_P9 LLWU_P14 LLWU_P10 PTD6/ PTE1 PTD3 PTC10 PTC9 PTC7 PTC2 PTC4/ LLWU_P15 LLWU_P8 PTC1/ PTC3/ PTD5 PTD2 PTD0 PTB19 LLWU_P6/ LLWU_P7 RTC_CLKIN USB0_DM VREGIN PTA0 PTA1 PTA3 PTB18 PTB17 PTC0 USB0_DP...
Page 119: System Modules
Chapter 10 Pinouts and Packaging 10.5.2 System modules Table 10-3. System signal descriptions Chip signal name Module signal Description name — Non-maskable interrupt NOTE: Driving the NMI signal low forces a non-maskable interrupt, if the NMI function is selected on the corresponding pin.
Page 120: Timer Modules
Module Signal Description Tables Table 10-6. ADC0 signal descriptions (continued) Chip signal name Module signal Description name VDDA Analog Power Supply VSSA Analog Ground EXTRG_IN ADHWT Hardware trigger This table presents the signal descriptions of the CMP0 module. Table 10-7. CMP0 signal descriptions Chip signal name Module signal Description...
Page 121: Communication Interfaces
Chapter 10 Pinouts and Packaging Table 10-11. TPM1 signal descriptions Chip signal name Module signal Description name TPM_CLKIN[1:0] TPM_EXTCLK External clock. TPM external clock can be selected to increment the TPM counter on every rising edge synchronized to the counter clock.
Page 122 Module Signal Description Tables Table 10-16. USB VREG Signal Descriptions Chip signal name Module signal Description name VOUT33 reg33_out Regulator output voltage VREGIN reg33_in Unregulated power supply Table 10-17. SPI0 signal descriptions Chip signal name Module signal Description name SPI0_MISO MISO Master Data In, Slave Data Out SPI0_MOSI...
Page 123 Chapter 10 Pinouts and Packaging Table 10-21. LPUART0 signal descriptions Chip signal name Module signal Description name LPUART0_TX Transmit data LPUART0_RX Receive data Table 10-22. LPUART1 signal descriptions Chip signal name Module signal Description name LPUART1_TX Transmit data LPUART1_RX Receive data Table 10-23.
Page 124: Human-Machine Interfaces (Hmi)
Module Signal Description Tables Table 10-25. FlexIO signal descriptions Chip signal name Module signal name Description FXIO0_Dx FXIO_Dn (n=0...7) Bidirectional FlexIO Shifter and Timer pin inputs/outputs 10.5.7 Human-machine interfaces (HMI) Table 10-26. GPIO Signal Descriptions Chip signal name Module signal Description name PTA[20:0]...
Page 125: Port Control And Interrupts (Port)
Chapter 11 Port Control and Interrupts (PORT) 11.1 Chip-specific PORT information The following table list registers that are not implemented in this device: Absolute address (hex) Register names Notes 4004_9020-4004_902C PORTA_PCR8, PORTA_PCR9, Not implemented in this device. PORTA_PCR10, and PORTA_PCR11 4004_9054-4004_907C PORTA_PCR21, PORTA_PCR22, PORTA_PCR23, PORTA_PCR24,...
Page 126: Port Control And Interrupt Summary
Port control and interrupt summary Absolute address (hex) Register names Notes PORTD_PCR26, PORTD_PCR27, PORTD_PCR28, PORTD_PCR29, PORTD_PCR30, and PORTD_PCR31 4004_D01C-4004_D03C PORTE_PCR7, PORTE_PCR8, PORTE_PCR9, PORTE_PCR10, PORTE_PCR11, PORTE_PCR12, PORTE_PCR13, PORTE_PCR14, and PORTE_PCR15 4004_D06C PORTE_PCR27 4004_D070 PORTE_PCR28 11.2 Port control and interrupt summary The following table provides more information regarding the Port Control and Interrupt configurations .
Page 127: Introduction
Chapter 11 Port Control and Interrupts (PORT) Table 11-1. Ports summary (continued) Feature Port A Port B Port C Port D Port E Pin mux at reset PTA0/PTA3/ ALT0 ALT0 ALT0 ALT0 PTA4=ALT7; Others=ALT0 Lock bit Interrupt and DMA request Digital glitch filter 1.
Page 128: Modes Of Operation
Overview • Asynchronous wake-up in low-power modes • Pin interrupt is functional in all digital pin muxing modes • Port control • Individual pull control fields with pullup, pulldown, and pull-disable support on selected pins • Individual drive strength field supporting high and low drive strength on selected pins •...
Page 129: External Signal Description
Chapter 11 Port Control and Interrupts (PORT) 11.5 External signal description The table found here describes the PORT external signal. Table 11-2. Signal properties Name Function Reset Pull PORTx[31:0] External interrupt NOTE Not all pins within each port are implemented on each device. 11.6 Detailed signal description The table found here contains the detailed signal description for the PORT interface.
Page 130 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_900C Pin Control Register n (PORTA_PCR3) See section 11.7.1/135 4004_9010 Pin Control Register n (PORTA_PCR4) See section 11.7.1/135 4004_9014 Pin Control Register n (PORTA_PCR5) See section...
Page 131 Chapter 11 Port Control and Interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_A00C Pin Control Register n (PORTB_PCR3) See section 11.7.1/135 4004_A010 Pin Control Register n (PORTB_PCR4) See section 11.7.1/135 4004_A014 Pin Control Register n (PORTB_PCR5)
Page 132 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_B00C Pin Control Register n (PORTC_PCR3) See section 11.7.1/135 4004_B010 Pin Control Register n (PORTC_PCR4) See section 11.7.1/135 4004_B014 Pin Control Register n (PORTC_PCR5) See section...
Page 133 Chapter 11 Port Control and Interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_C00C Pin Control Register n (PORTD_PCR3) See section 11.7.1/135 4004_C010 Pin Control Register n (PORTD_PCR4) See section 11.7.1/135 4004_C014 Pin Control Register n (PORTD_PCR5) See section...
Page 134 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_D00C Pin Control Register n (PORTE_PCR3) See section 11.7.1/135 4004_D010 Pin Control Register n (PORTE_PCR4) See section 11.7.1/135 4004_D014 Pin Control Register n (PORTE_PCR5) See section 11.7.1/135...
Page 135: Pin Control Register N (Portx_Pcrn)
Chapter 11 Port Control and Interrupts (PORT) 11.7.1 Pin Control Register n (PORTx_PCRn) NOTE See the Signal Multiplexing and Pin Assignment chapter for the reset value of this device. See the GPIO Configuration section for details on the available functions for each pin. Do not modify pin configuration registers associated with pins not available in your selected package.
Page 136 Memory map and register definition PORTx_PCRn field descriptions (continued) Field Description Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag.
Page 137 Chapter 11 Port Control and Interrupts (PORT) PORTx_PCRn field descriptions (continued) Field Description Drive Strength Enable This field is read-only for pins that do not support a configurable drive strength. Drive strength configuration is valid in all digital pin muxing modes. Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
Page 138: Global Pin Control Low Register (Portx_Gpclr)
Memory map and register definition 11.7.2 Global Pin Control Low Register (PORTx_GPCLR) Only 32-bit writes are supported to this register. Address: Base address + 80h offset GPWE GPWD Reset PORTx_GPCLR field descriptions Field Description 31–16 Global Pin Write Enable GPWE Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD.
Page 139: Interrupt Status Flag Register (Portx_Isfr)
Chapter 11 Port Control and Interrupts (PORT) 11.7.4 Interrupt Status Flag Register (PORTx_ISFR) The corresponding bit is read only for pins that do not support interrupt generation. The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt Status Flag for each pin is also visible in the corresponding Pin Control Register, and each flag can be cleared in either location.
Page 140: Global Pin Control
Functional description • Passive input filter enable on selected pins • Pin Muxing mode The functions apply across all digital pin muxing modes and individual peripherals do not override the configuration in the Pin Control register. For example, if an I C function is enabled on a pin, that does not override the pullup configuration for that pin.
Page 141 Chapter 11 Port Control and Interrupts (PORT) Each pin can be individually configured for any of the following external interrupt modes: • Interrupt disabled, default out of reset • Active high level sensitive interrupt • Active low level sensitive interrupt •...
Page 142 Functional description KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 143: System Integration Module (Sim)
Chapter 12 System Integration Module (SIM) 12.1 Chip-specific SIM information 12.1.1 COP clocks The multiple clock inputs for the COP are: • 1 kHz clock • bus clock • 8 MHz or 2 MHz internal reference clock • external crystal 12.2 Introduction The system integration module (SIM) provides system control and chip configuration registers.
Page 144: Memory Map And Register Definition
Memory map and register definition 12.3 Memory map and register definition The SIM module contains many bitfields for selecting the clock source and dividers for various module clocks. NOTE The SIM registers can be written only in supervisor mode. In user mode, write accesses are blocked and will result in a bus error.
Page 145: System Options Register 1 (Sim_Sopt1)
Chapter 12 System Integration Module (SIM) 12.3.1 System Options Register 1 (SIM_SOPT1) NOTE The SOPT1 register is only reset on POR or LVD. Address: 4004_7000h base + 0h offset = 4004_7000h OSC32KSEL OSC32KOUT Reset Reserved Reset * Notes: • Reserved field: Device specific value. SIM_SOPT1 field descriptions Field Description...
Page 146: Sopt1 Configuration Register (Sim_Sopt1Cfg)
Memory map and register definition SIM_SOPT1 field descriptions (continued) Field Description 19–18 32K Oscillator Clock Select OSC32KSEL Selects the 32 kHz clock source (ERCLK32K) for RTC and LPTMR. This field is reset only on POR/LVD. System oscillator (OSC32KCLK) Reserved RTC_CLKIN LPO 1kHz 17–16 32K oscillator clock output...
Page 147 Chapter 12 System Integration Module (SIM) SIM_SOPT1CFG field descriptions Field Description 31–27 This field is reserved. Reserved This read-only field is reserved and always has the value 0. USB voltage regulator stop standby write enable USSWE Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written. This register bit clears after a write to USBSSTBY.
Page 148: System Options Register 2 (Sim_Sopt2)
Memory map and register definition 12.3.3 System Options Register 2 (SIM_SOPT2) SOPT2 contains the controls for selecting many of the module clock source options on this device. See the Clock Distribution chapter for more information including clocking diagrams and definitions of device clocks. Address: 4004_7000h base + 1004h offset = 4004_8004h TPMSRC FLEXIOSRC...
Page 149 Chapter 12 System Integration Module (SIM) SIM_SOPT2 field descriptions (continued) Field Description Clock disabled IRC48M clock OSCERCLK clock MCGIRCLK clock 23–22 FlexIO Module Clock Source Select FLEXIOSRC Selects the clock source for the FlexIO transmit and receive clock. Clock disabled IRC48M clock OSCERCLK clock MCGIRCLK clock...
Page 150: System Options Register 4 (Sim_Sopt4)
Memory map and register definition 12.3.4 System Options Register 4 (SIM_SOPT4) Address: 4004_7000h base + 100Ch offset = 4004_800Ch Reset Reset SIM_SOPT4 field descriptions Field Description 31–27 This field is reserved. Reserved This read-only field is reserved and always has the value 0. TPM2 External Clock Pin Select TPM2CLKSEL Selects the external pin used to drive the clock to the TPM2 module.
Page 151: System Options Register 5 (Sim_Sopt5)
Chapter 12 System Integration Module (SIM) SIM_SOPT4 field descriptions (continued) Field Description 23–21 This field is reserved. Reserved This read-only field is reserved and always has the value 0. TPM2 Channel 0 Input Capture Source Select TPM2CH0SRC Selects the source for TPM2 channel 0 input capture. NOTE: When TPM2 is not in input capture mode, clear this field.
Page 152 Memory map and register definition SIM_SOPT5 field descriptions Field Description 31–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. UART2 Open Drain Enable UART2ODE Open drain is disabled on UART2...
Page 153: System Options Register 7 (Sim_Sopt7)
Chapter 12 System Integration Module (SIM) 12.3.6 System Options Register 7 (SIM_SOPT7) Address: 4004_7000h base + 1018h offset = 4004_8018h Reset ADC0TRGSEL Reset SIM_SOPT7 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. ADC0 Alternate Trigger Enable ADC0ALTTRGEN Enables alternative conversion triggers for ADC0.
Page 154: System Device Identification Register (Sim_Sdid)
Memory map and register definition SIM_SOPT7 field descriptions (continued) Field Description ADC0TRGSEL ADC0 Trigger Select Selects 1 of 16 peripherals to initiate an ADC conversion via the ADHWDT input, when ADC0ALTTRGEN =1, else is ignored by ADC0. 0000 External trigger pin input (EXTRG_IN) 0001 CMP0 output 0010...
Page 155 Chapter 12 System Integration Module (SIM) SIM_SDID field descriptions (continued) Field Description 0011 KL33 0100 KL43 27–24 Kinetis Sub-Family ID SUBFAMID Specifies the Kinetis sub-family of the device. 0011 KLx3 Subfamily 23–20 Kinetis Series ID SERIESID Specifies the Kinetis family of the device. 0001 KL family 19–16...
Page 156: System Clock Gating Control Register 4 (Sim_Scgc4)
Memory map and register definition 12.3.8 System Clock Gating Control Register 4 (SIM_SCGC4) Address: 4004_7000h base + 1034h offset = 4004_8034h SPI1 SPI0 VREF Reset I2C1 I2C0 Reset SIM_SCGC4 field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 1. 27–24 This field is reserved.
Page 157 Chapter 12 System Integration Module (SIM) SIM_SCGC4 field descriptions (continued) Field Description Clock disabled Clock enabled USB Clock Gate Control USBFS This bit controls the clock gate to the USB module. Clock disabled Clock enabled 17–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 158: System Clock Gating Control Register 5 (Sim_Scgc5)
Memory map and register definition 12.3.9 System Clock Gating Control Register 5 (SIM_SCGC5) Address: 4004_7000h base + 1038h offset = 4004_8038h Reset Reset SIM_SCGC5 field descriptions Field Description FlexIO Module FLEXIO This bit controls the clock gate to the FlexIO Module. Clock disabled Clock enabled 30–22...
Page 159 Chapter 12 System Integration Module (SIM) SIM_SCGC5 field descriptions (continued) Field Description Clock disabled Clock enabled Port D Clock Gate Control PORTD Controls the clock gate to the Port D module. Clock disabled Clock enabled Port C Clock Gate Control PORTC Controls the clock gate to the Port C module.
Page 160: System Clock Gating Control Register 6 (Sim_Scgc6)
Memory map and register definition 12.3.10 System Clock Gating Control Register 6 (SIM_SCGC6) Address: 4004_7000h base + 103Ch offset = 4004_803Ch Reset Reset SIM_SCGC6 field descriptions Field Description DAC0 Clock Gate Control DAC0 This bit controls the clock gate to the DAC0 module. Clock disabled Clock enabled This field is reserved.
Page 161 Chapter 12 System Integration Module (SIM) SIM_SCGC6 field descriptions (continued) Field Description TPM1 Clock Gate Control TPM1 Controls the clock gate to the TPM1 module. Clock disabled Clock enabled TPM0 Clock Gate Control TPM0 Controls the clock gate to the TPM0 module. Clock disabled Clock enabled PIT Clock Gate Control...
Page 162: System Clock Gating Control Register 7 (Sim_Scgc7)
Memory map and register definition 12.3.11 System Clock Gating Control Register 7 (SIM_SCGC7) Address: 4004_7000h base + 1040h offset = 4004_8040h Reset Reset SIM_SCGC7 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. DMA Clock Gate Control Controls the clock gate to the DMA module.
Page 163 Chapter 12 System Integration Module (SIM) SIM_CLKDIV1 field descriptions Field Description 31–28 Clock 1 Output Divider value OUTDIV1 Sets the divide value for the core/system clock, as well as the bus/flash clocks. At the end of reset, it is loaded with 0000 (divide by one), 0001 (divide by two), 0011 (divide by four), or 0111 (divide by eight) depending on the setting of the FTFA_FOPT[LPBOOT] (See Table 6-2).
Page 164: Flash Configuration Register 1 (Sim_Fcfg1)
Memory map and register definition 12.3.13 Flash Configuration Register 1 (SIM_FCFG1) Address: 4004_7000h base + 104Ch offset = 4004_804Ch PFSIZE Reset Reset * Notes: • PFSIZE field: Device specific value. SIM_FCFG1 field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 165: Flash Configuration Register 2 (Sim_Fcfg2)
Chapter 12 System Integration Module (SIM) SIM_FCFG1 field descriptions (continued) Field Description 23–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Flash Doze FLASHDOZE When set, flash memory is disabled for the duration of Doze mode. This field must be clear during VLP modes.
Page 166: Unique Identification Register Mid-High (Sim_Uidmh)
Memory map and register definition SIM_FCFG2 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 30–24 Max Address lock MAXADDR0 This field concatenated with 13 trailing zeros indicates the first invalid address of program flash (block 0). For example, if MAXADDR0 = 0x10, the first invalid address of program flash (block 0) is 0x0002_0000.
Page 167: Unique Identification Register Mid Low (Sim_Uidml)
Chapter 12 System Integration Module (SIM) 12.3.16 Unique Identification Register Mid Low (SIM_UIDML) Address: 4004_7000h base + 105Ch offset = 4004_805Ch Reset * Notes: • UID field: Device specific value. SIM_UIDML field descriptions Field Description Unique Identification Unique identification for the device. 12.3.17 Unique Identification Register Low (SIM_UIDL) Address: 4004_7000h base + 1060h offset = 4004_8060h Reset...
Page 168: Cop Control Register (Sim_Copc)
Memory map and register definition 12.3.18 COP Control Register (SIM_COPC) All of the bits in this register can be written only once after a reset, writing this register will also reset the COP counter. Address: 4004_7000h base + 1100h offset = 4004_8100h Reset COPCLKSEL COPT...
Page 169: Service Cop (Sim_Srvcop)
Chapter 12 System Integration Module (SIM) SIM_COPC field descriptions (continued) Field Description COP timeout after 2 cycles for short timeout or 2 cycles for long timeout COP timeout after 2 cycles for short timeout or 2 cycles for long timeout COP timeout after 2 cycles for short timeout or 2 cycles for long timeout...
Page 170: Cop Watchdog Operation
Functional description 12.4.1 COP watchdog operation The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), the application software must reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter before it times out, a system reset is generated to force the system back to a known starting point.
Page 171 Chapter 12 System Integration Module (SIM) Table 12-1. COP configuration options (continued) Control bits Clock COP window opens COP overflow source count SIM_COPC[COPCLK SIM_COPC[COPCLK SIM_COPC[COP (SIM_COPC[COPW]=1) SEL] 8/2 MHz cycles 6,144 cycles cycles 8/2 MHz cycles 49,152 cycles cycles 8/2 MHz cycles 196,608 cycles cycles...
Page 172 Functional description If the selected clock is not the 1 kHz clock source, the COP counter does not increment while the microcontroller is in Debug mode or while the system is in Stop (including VLPS or LLS) mode. The COP counter resumes when the microcontroller exits Debug or Stop mode.
Page 173: Chip-Specific Information
Chapter 13 Kinetis ROM Bootloader 13.1 Chip-Specific Information This device has various peripherals (UART, I2C, SPI , USB) supported by the Kinetis ROM Bootloader. To use an interface for bootloader communications, the peripheral must be enabled in the BCA, as shown in Table 13-3.
Page 174 Introduction The Kinetis Bootloader’s main task is to provision the internal flash memory with an embedded firmware image during manufacturing, or at any time during the life of the Kinetis device. The Kinetis Bootloader does the provisioning by acting as a slave device, and listening to various peripheral ports where a master can start communication.
Page 175: Functional Description
Chapter 13 Kinetis ROM Bootloader Table 13-2. Commands supported by the Kinetis Bootloader in ROM Command Description When flash security is enabled, then this command is Execute Run user application code that never returns control to Not supported the bootloader FlashEraseAll Erase the entire flash array Not supported...
Page 176: The Kinetis Bootloader Configuration Area (Bca)
Functional Description 13.3.2 The Kinetis Bootloader Configuration Area (BCA) The Kinetis Bootloader reads data from the Bootloader Configuration Area (BCA) to configure various features of the bootloader. The BCA resides in flash memory at offset 0x3C0, and provides all of the parameters needed to configure the Kinetis Bootloader operation.
Page 177: Start-Up Process
Chapter 13 Kinetis ROM Bootloader Table 13-3. Configuration Fields for the Kinetis Bootloader (continued) Offset Size (bytes) Configuration Field Description 0x1F pad byte 0x24 Reserved 0x28 Reserved 0x30 Reserved 0x34 Reserved NOTE The flash sector containing the BCA should not be located in the execute-only region, because the Kinetis bootloader cannot read an execute-only region.
Page 178 Functional Description • The BOOTCFG0 pin is asserted. The pin must be configured as BOOTCFG0 by setting the BOOTPIN_OPT bit of FOPT to 0. • A user applications running on flash or RAM calls into the Kinetis Bootloader entry point address in ROM, to start Kinetis Bootloader execution. The FOPT[BOOTSRC_SEL] determines the boot source.
Page 179 Chapter 13 Kinetis ROM Bootloader Shutdown all Jump to user Enter bootloader Peripherals application Init hardware Timeout Check enabled and has Timeout occurred? Load user-config data SPIn entered Configure clocks interrupt state? Init Flash, Property and Memory interfaces I2Cn entered Shutdown unused interrupt state? Peripherals...
Page 180: Clock Configuration
Functional Description 13.3.4 Clock Configuration By default, the bootloader does not modify clocks. The Kinetis Bootloader in ROM will use the clock configuration of the chip out of reset unless the clock configuration bits in the FOPT register are cleared, or if a USB peripheral is enabled. •...
Page 181: Bootloader Protocol
Chapter 13 Kinetis ROM Bootloader Example code to get the entry pointer address from the ROM and start the bootloader. NOTE This entry must be called in supervisor (privileged) mode. // Variables uint32_t runBootloaderAddress; void (*runBootloader)(void * arg); // Read the function address from the ROM API tree. runBootloaderAddress = **(uint32_t **)(0x1c00001c);...
Page 182 Functional Description 13.3.6.1 Command with no data phase The protocol for a command with no data phase contains: • Command packet (from host) • Generic response command packet (to host) Target Host Command Process command Response Figure 13-3. Command with No Data Phase 13.3.6.2 Command with incoming data phase The protocol for a command with an incoming data phase contains: •...
Page 183 Chapter 13 Kinetis ROM Bootloader Target Host Command Process command Initial Response Data packet Process data Final data packet Process data Final Response Figure 13-4. Command with incoming data phase NOTE • The host may not send any further packets while it (the host) is waiting for the response to a command.
Page 184 Functional Description kStatus_AbortDataPhase. The host may abort the data phase early by sending a zero-length data packet. • The final Generic Response packet sent after the data phase includes the status for the entire operation. 13.3.6.3 Command with outgoing data phase The protocol for a command with an outgoing data phase contains: •...
Page 185 Chapter 13 Kinetis ROM Bootloader Target Host Command Process command Initial Response Data packet Process data Final data packet Process data Final Response Figure 13-5. Command with outgoing data phase NOTE • For the outgoing data phase sequence above, the data phase is really considered part of the response command.
Page 186: Bootloader Packet Types
Functional Description • Data phases may be aborted by the host sending the final Generic Response early with a status of kStatus_AbortDataPhase. The sending side may abort the data phase early by sending a zero-length data packet. • The final Generic Response packet sent after the data phase includes the status for the entire operation.
Page 187 Chapter 13 Kinetis ROM Bootloader Target Host Ping Packet 0x5a 0xa6 Target executes UART autobaud if necessary PingResponse Packet : 0x5a 0xa7 0x00 0x02 0x01 0x50 0x00 0x00 0xaa 0xea Figure 13-6. Ping Packet Protocol Sequence 13.3.7.2 Ping Response Packet The target (Kinetis Bootloader) sends a Ping Response packet back to the host after receiving a Ping packet.
Page 188 Functional Description 13.3.7.3 Framing Packet The framing packet is used for flow control and error detection, and it (the framing packet) wraps command and data packets as well. The framing packet described in this section is used for serial peripherals including LPUART, I2C and SPI.
Page 189 Chapter 13 Kinetis ROM Bootloader Table 13-10. packetType Field (continued) packetType Name Description 0xA6 kFramingPacketType_Ping Sent to verify the other side is alive. Also used for UART autobaud. 0xA7 kFramingPacketType_PingResponse A response to Ping; contains the framing protocol version number and options. CRC16 algorithm: uint16_t crc16_update(const uint8_t * src, uint32_t lengthInBytes) uint32_t crc = 0;...
Page 190 Functional Description 13.3.7.4 Command packet The command packet carries a 32-bit command header and a list of 32-bit parameters. Table 13-11. Command Packet Format Command Packet Format (32 bytes) Command Header (4 bytes) 28 bytes for Parameters (Max 7 parameters) Flags Rsvd Param...
Page 191 Chapter 13 Kinetis ROM Bootloader Table 13-13. Commands that are supported (continued) Command Name 0x0E Reserved 0x0F Reserved 0x10 Reserved 0x11 Reserved Table 13-14. Responses that are supported Response Name 0xA0 GenericResponse 0xA7 GetPropertyResponse (used for sending responses to GetProperty command only) 0xA3 ReadMemoryResponse (used for sending responses to ReadMemory command only)
Page 192 Functional Description 13.3.7.6 Response packet The responses are carried using the same command packet format wrapped with framing packet data. Types of responses include: • GenericResponse • GetPropertyResponse • ReadMemoryResponse GenericResponse: After the Kinetis Bootloader has processed a command, the bootloader will send a generic response with status and command tag information to the host.
Page 193: Bootloader Command Api
Chapter 13 Kinetis ROM Bootloader ReadMemoryResponse: The ReadMemoryResponse packet is sent by the target in response to the host sending a ReadMemory command. The ReadMemoryResponse packet contains the framing packet data and the command packet data, with the command/response tag set to a ReadMemoryResponse tag value (0xA3), the flags field set to kCommandFlag_HasDataPhase (1).
Page 194 Functional Description Table 13-18. Parameters for Execute Command Byte # Command 0 - 3 Jump address 4 - 7 Argument word 8 - 11 Stack pointer address The Execute command has no data phase. Response: Before executing the Execute command, the target (Kinetis Bootloader) will validate the parameters and return a GenericResponse packet with a status code either set to kStatus_Success or an appropriate error status code.
Page 195 Chapter 13 Kinetis ROM Bootloader Table 13-19. Reset Command Packet Format (Example) (continued) Reset Parameter Value crc16 0x6F 0x46 Command packet commandTag 0x0B - reset flags 0x00 reserved 0x00 parameterCount 0x00 The Reset command has no data phase. Response: The target (Kinetis Bootloader) will return a GenericResponse packet with status code set to kStatus_Success, before resetting the chip.
Page 196 Functional Description Target Host GetProperty: Property tag = 0x01 0x5a a4 08 00 73 d4 07 00 00 01 01 00 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 07 7a a7 00 00 02 00 00 00 00 00 00 01 4 b ACK: 0x5a a1 Figure 13-8.
Page 197 Chapter 13 Kinetis ROM Bootloader Table 13-22. GetProperty Response Packet Format (Example) (continued) GetPropertyResponse Parameter Value crc16 0x07 0x7a Command packet responseTag 0xA7 flags 0x00 reserved 0x00 parameterCount 0x02 status 0x00000000 propertyValue 0x0000014b - CurrentVersion 13.3.8.4 SetProperty command The SetProperty command is used to change or alter the values of the properties or options in the Kinetis Bootloader ROM.
Page 198 Functional Description Target Host SetProperty: Property tag = 10, Property Value = 1 0x5a a4 0 c 00 67 8d 0c 00 00 02 0 a 00 00 00 01 00 00 00 ACK : 0x5a a1 Process command GenericResponse: 0x5a a4 00 9 e 10 a0 00 0c 02 00 00 00 00 0c 00 00 00 ACK: 0x5a a1...
Page 199 Chapter 13 Kinetis ROM Bootloader 13.3.8.5 FlashEraseAll command The FlashEraseAll command performs an erase of the entire flash memory. If any flash regions are protected, then the FlashEraseAll command will fail and return an error status code. Executing the FlashEraseAll command will release flash security if it (flash security) was enabled, by setting the FTFA_FSEC register.
Page 200 Functional Description Response: The target (Kinetis Bootloader ) will return a GenericResponse packet with status code either set to kStatus_Success for successful execution of the command, or set to an appropriate error status code. 13.3.8.6 FlashEraseRegion command The FlashEraseRegion command performs an erase of one or more sectors of the flash memory or a specified range of flash within the connected SPI flash devices.
Page 201 Chapter 13 Kinetis ROM Bootloader Table 13-28. FlashEraseRegion Command Packet Format (Example) FlashEraseRegion Parameter Value Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0xF9 0x A6 Command packet commandTag 0x02, kCommandTag_FlashEraseRegion flags 0x00 reserved 0x00 parameterCount 0x02 startAddress 0x00 0x00 0x00 0x00 (0x0000_0000)
Page 202 Functional Description Target Host FlashEraseAllUnsecure 0x5a a4 04 00 f6 61 0d 00 cc 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 61 2c a0 00 04 02 00 00 00 00 0d 00 00 00 ACK: 0x5a a1 Figure 13-12.
Page 203 Chapter 13 Kinetis ROM Bootloader Table 13-31. Parameters for FlashSecurityDisable Command Byte # Command 0 - 3 Backdoor key low word 4 - 7 Backdoor key high word Target Host FlashSecureDisable , with backdoor key 0102030405060708 0x5a a4 0c 00 43 7b 06 00 00 04 03 02 01 08 07 06 05 ACK: 0x5a a1 Process command...
Page 204 Functional Description 13.3.8.9 WriteMemory command The WriteMemory command writes data provided in the data phase to a specified range of bytes in memory (flash or RAM). However, if flash protection is enabled, then writes to protected sectors will fail. Special care must be taken when writing to flash. •...
Page 205 Chapter 13 Kinetis ROM Bootloader Target Host WriteMemory : startAddress = 0x20000400, byteCount = 0x64 0x5a a4 0c 00 06 5 a 04 00 00 02 00 04 00 20 64 00 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 a0 0e 04 01 00 02 00 04 00 20 40 00 00 00 ACK: 0x5a a1 Data packet :...
Page 206 Functional Description Data Phase: The WriteMemory command has a data phase; the host will send data packets until the number of bytes of data specified in the byteCount parameter of the WriteMemory command are received by the target. Response: The target (Kinetis Bootloader ) will return a GenericResponse packet with a status code set to kStatus_Success upon successful execution of the command, or to an appropriate error status code.
Page 207 Chapter 13 Kinetis ROM Bootloader Target Host readMemory : startAddress = 0x20000400, byteCount = 100 0x5a a4 0c 00 1d 23 03 00 00 02 00 04 00 20 64 00 00 00 ACK: 0x5a a1 Process command Generic response for command: 0x5a a4 0c 00 27 f6 a3 01 00 02 00 00 00 00 64 00 00 00 ACK: 0x5a a1 Data packet :...
Page 208: Bootloader Exit State
Functional Description Data Phase: The ReadMemory command has a data phase. Since the target (Kinetis Bootloader) works in slave mode, the host need pull data packets until the number of bytes of data specified in the byteCount parameter of ReadMemory command are received by host.
Page 209: Peripherals Supported
Chapter 13 Kinetis ROM Bootloader • Affected pin mux: • LPUART0(PTA1, PTA2) • I2C0(PTB0, PTB1) • SPI0(PTC4, PTC5, PTC6, PTC7) • Affected peripheral registers: • LPUART and LPUART clock source (SIM_SOPT2_PLLFLLSEL = 3) • SPI • I2C You must re-configure the corresponding register to the expected value, instead of relying on the default value.
Page 210 Peripherals Supported • An outgoing packet is read by the host with a selected I2C slave address and the direction bit is set as read. • 0x00 will be sent as the response to host if the target is busy with processing or preparing data.
Page 211: Spi Peripheral
Chapter 13 Kinetis ROM Bootloader Fetch Response Read 1 byte from target Read payload data from target Reached 0x5A maximum received? retries? Set payload length Payload length to maximum less than supported Read 1 byte supported length length? from target Read Read payload length...
Page 212 Peripherals Supported • Processing incoming packet • Preparing outgoing data • Received invalid data The SPI bus configuration is: • Phase = 1; data is sampled on rising edges • Polarity = 1; idle is high • MSB is transmitted first For any transfer where the target does not have actual data to send, the target (slave) is responsible for ensuring that 0x00 bytes will be returned to the host (master).
Page 213: Usb Peripheral
Chapter 13 Kinetis ROM Bootloader Report an error Fetch ACK Send 0x00 to 0xA2 shift out 1 byte Process NAK received? from target Reached maximum retries? Send 0x00 to 0x5A 0xA1 shift out 1 byte received? received? from target Report a Next action timeout error Figure 13-20.
Page 214 Peripherals Supported USB HID does not use framing packets; instead the packetization inherent in the USB protocol itself is used. The ability for the device to NAK Out transfers (until they can be received) provides the required flow control; the built-in CRC of each USB packet provides the required error detection.
Page 215 Chapter 13 Kinetis ROM Bootloader USB_STR_3}; g_string_desc_size[4] = { sizeof(USB_STR_0), sizeof(USB_STR_1), sizeof(USB_STR_2), sizeof(USB_STR_3)}; You can make your own structure of USB_STR_1, USB_STR_2, USB_STR_3: • USB_STR_1 is used for the manufacturer string. • USB_STR_2 is used for the product string. • USB_STR_3 is used for the serial number string. By default, the 3 strings are defined as below: USB_STR_1[] = sizeof(USB_STR_1),...
Page 216 Peripherals Supported 'e',0 USB_STR_3[] = sizeof(USB_STR_3), USB_STRING_DESCRIPTOR, '0',0, '1',0, '2',0, '3',0, '4',0, '5',0, '6',0, '7',0, '8',0, '9',0, 'A',0, 'B',0, 'C',0, 'D',0, 'E',0, 'F',0 13.4.3.3 Endpoints The HID peripheral uses 3 endpoints: • Control (0) • Interrupt IN (1) • Interrupt OUT (2) The Interrupt OUT endpoint is optional for HID class devices, but the Kinetis Bootloader uses it as a pipe, where the firmware can NAK send requests from the USB host.
Page 217: Get/Setproperty Command Properties
Chapter 13 Kinetis ROM Bootloader Usage Min Usage Max Logical Min Logical Max Report Size Report Count Each report has a maximum size of 34 bytes. This is derived from the minimum bootloader packet size of 32 bytes, plus a 2-byte report header that indicates the length (in bytes) of the packet sent in the report.
Page 218 Get/SetProperty Command Properties Table 13-36. Properties used by Get/SetProperty Commands, sorted by Value Property Writable Tag Value Size Descripion CurrentVersion Current bootloader version. AvailablePeripherals The set of peripherals supported on this chip. FlashStartAddress Start address of program flash. FlashSizeInBytes Size in bytes of program flash. FlashSectorSize The size in bytes of one sector of program flash.
Page 219: Property Definitions
Chapter 13 Kinetis ROM Bootloader 13.5.1 Property Definitions Get/Set property definitions are provided in this section. 13.5.1.1 CurrentVersion Property The value of this property is a 4-byte structure containing the current version of the bootloader. Table 13-37. Fields of CurrentVersion property: Bits [31:24] [23:16]...
Page 220: Kinetis Bootloader Status Error Codes
Kinetis Bootloader Status Error Codes Table 13-39. Command bits: [31: [16] [15] [14] [13] [12] [11] [10] Command 13.6 Kinetis Bootloader Status Error Codes This section describes the status error codes that the Kinetis Bootloader returns to the host. Table 13-40. Kinetis Bootloader Status Error Codes, sorted by Value Error Code Value Description...
Page 221: Bootloader Errata
Chapter 13 Kinetis ROM Bootloader Table 13-40. Kinetis Bootloader Status Error Codes, sorted by Value (continued) Error Code Value Description kStatus_SPI_Busy SPI instance is already busy performing a transfer. kStatus_SPI_NoTransferInProgress Attempt to abort a transfer when no transfer was in progress. kStatus_UnknownCommand 10000 The requested command value is undefined.
Page 222 Bootloader errata 1. PORT clock gate, pin mux and peripheral registers are not reset to default values on ROM exit Description • Affected PORT clock gates: PORTA, PORTB, PORTC, PORTD and PORTE (SIM_SCGC5_PORTA, SIM_SCGC5_PORTB, SIM_SCGC5_PORTC, SIM_SCGC5_PORTD and SIM_SCGC5_PORTE are enabled) •...
Page 223: System Mode Controller (Smc)
Chapter 14 System Mode Controller (SMC) 14.1 Chip-specific SMC information This device does not support VLLS2 power mode. Ignore the VLLS2 in the following sections. 14.2 Introduction The System Mode Controller (SMC) is responsible for sequencing the system into and out of all low-power Stop and Run modes.
Page 224 Modes of operation The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, Wait, and Stop are the common terms used for the primary operating modes of Freescale microcontrollers. The following table shows the translation between the ARM CPU modes and the Freescale MCU power modes.
Page 225: Memory Map And Register Descriptions
Chapter 14 System Mode Controller (SMC) Table 14-1. Power modes (continued) Mode Description VLPW The core clock is gated off. The system, bus, and flash clocks continue to operate, although their maximum frequency is restricted. See the Power Management chapter for details on the maximum allowable frequencies.
Page 226: Power Mode Protection Register (Smc_Pmprot)
Memory map and register descriptions SMC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_E000 Power Mode Protection register (SMC_PMPROT) 14.4.1/226 4007_E001 Power Mode Control register (SMC_PMCTRL) 14.4.2/227 4007_E002 Stop Control Register (SMC_STOPCTRL) 14.4.3/228 4007_E003 Power Mode Status register (SMC_PMSTAT)
Page 227: Power Mode Control Register (Smc_Pmctrl)
Chapter 14 System Mode Controller (SMC) SMC_PMPROT field descriptions (continued) Field Description VLPR, VLPW, and VLPS are not allowed. VLPR, VLPW, and VLPS are allowed. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Allow Low-Leakage Stop Mode ALLS Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter...
Page 228: Stop Control Register (Smc_Stopctrl)
Memory map and register descriptions SMC_PMCTRL field descriptions Field Description This field is reserved. Reserved This bit is reserved for future expansion and should always be written zero. 6–5 Run Mode Control RUNM When written, causes entry into the selected run mode. Writes to this field are blocked if the protection level has not been enabled using the PMPROT register.
Page 229 Chapter 14 System Mode Controller (SMC) NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information.
Page 230: Power Mode Status Register (Smc_Pmstat)
Functional description 14.4.4 Power Mode Status register (SMC_PMSTAT) PMSTAT is a read-only, one-hot register which indicates the current power mode of the system. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS.
Page 231 Chapter 14 System Mode Controller (SMC) Any RESET VLPW VLPR WAIT STOP VLPS VLLS 3, 1, 0 Figure 14-1. Power mode state diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 14-2. Power mode transition triggers Transition # From Trigger conditions...
Page 232 Functional description Table 14-2. Power mode transition triggers (continued) Transition # From Trigger conditions Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note. STOP Interrupt or Reset VLPR The core, system, bus and flash clock frequencies and MCG clocking mode are restricted in this mode.
Page 233: Power Mode Entry/Exit Sequencing
Chapter 14 System Mode Controller (SMC) Table 14-2. Power mode transition triggers (continued) Transition # From Trigger conditions LLSx PMPROT[ALLS]=1, PMCTRL[STOPM]=011, STOPCTRL[LLSM]=x (LLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. LLSx Wakeup from enabled LLWU input source or RESET pin.
Page 234: Run Modes
Functional description 14.5.2.2 Stop mode exit sequence Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR): 1. The on-chip regulator in the PMC and internal power switches are restored. 2.
Page 235 Chapter 14 System Mode Controller (SMC) 14.5.3.1 RUN mode This is the normal operating mode for the device. This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR): •...
Page 236: Wait Modes
Functional description To reenter Normal Run mode, clear PMCTRL[RUNM]. PMSTAT is a read-only status register that can be used to determine when the system has completed an exit to RUN mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at full speed in any clock mode.
Page 237: Stop Modes
Chapter 14 System Mode Controller (SMC) When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. A system reset will cause an exit from VLPW mode, returning the device to normal RUN mode.
Page 238 Functional description A module capable of providing an asynchronous interrupt to the device takes the device out of STOP mode and returns the device to normal RUN mode. Refer to the device's Power Management chapter for peripheral, I/O, and memory operation in STOP mode. When an interrupt request occurs, the CPU exits STOP mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine.
Page 239 Chapter 14 System Mode Controller (SMC) After wakeup from LLS, the device returns to normal RUN mode with a pending LLWU module interrupt. In the LLWU interrupt service routine (ISR), the user can poll the LLWU module wake-up flags to determine the source of the wakeup. NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully...
Page 240: Debug In Low Power Modes
Functional description An asserted RESET pin will cause an exit from any VLLS mode, returning the device to normal RUN mode. When exiting VLLS via the RESET pin, RCM_SRS[PIN] and RCM_SRS[WAKEUP] are set. 14.5.6 Debug in low power modes When the MCU is secure, the device disables/limits debugger operation. When the MCU is unsecure, the ARM debugger can assert two power-up request signals: •...
Page 241: Power Management Controller (Pmc)
Chapter 15 Power Management Controller (PMC) 15.1 Introduction The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), and low voltage detect system (LVD). AN4503: Power Management for Kinetis MCUs for further details on using the PMC.
Page 242: Lvd Reset Operation
Low-voltage detect (LVD) system when the supply voltage falls below the selected trip point (VLVD). LVDSC1[LVDF] is cleared by writing 1 to LVDSC1[LVDACK], but only if the internal supply has returned above the trip point; otherwise, LVDSC1[LVDF] remains set. • The Low Voltage Warning Flag (LVWF) in the Low Voltage Status and Control 2 Register (LVDSC2[LVWF]) operates in a level sensitive manner.
Page 243: I/O Retention
Chapter 15 Power Management Controller (PMC) • Two mid-levels: V and V LVW3 LVW2 • Lowest: V LVW1 15.4 I/O retention When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full regulation, and releases the logic from state retention mode.
Page 244: Low Voltage Detect Status And Control 1 Register (Pmc_Lvdsc1)
Memory map and register descriptions 15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) This register contains status and control bits to support the low voltage detect function. This register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
Page 245: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
Chapter 15 Power Management Controller (PMC) PMC_LVDSC1 field descriptions (continued) Field Description Low-Voltage Detect Reset Enable LVDRE This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored. LVDF does not generate hardware resets Force an MCU reset when LVDF = 1 3–2 This field is reserved.
Page 246: Regulator Status And Control Register (Pmc_Regsc)
Memory map and register descriptions PMC_LVDSC2 field descriptions Field Description Low-Voltage Warning Flag LVWF This read-only status field indicates a low-voltage warning event. LVWF is set when V transitions Supply below the trip point, or after reset and V is already below V .
Page 247 Chapter 15 Power Management Controller (PMC) Address: 4007_D000h base + 2h offset = 4007_D002h Read ACKISO REGONS Reserved BGEN Reserved BGBE Write Reset PMC_REGSC field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 248 Memory map and register descriptions KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 249: Miscellaneous Control Module (Mcm)
Chapter 16 Miscellaneous Control Module (MCM) 16.1 Introduction The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 16.1.1 Features The MCM includes the following features: • Program-visible information on the platform configuration • Crossbar master arbitration policy selection •...
Page 250: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
Memory map/register descriptions 16.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) PLASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the device’s crossbar switch. Address: F000_3000h base + 8h offset = F000_3008h Read Write Reset MCM_PLASC field descriptions Field Description 15–8...
Page 251: Platform Control Register (Mcm_Placr)
Chapter 16 Miscellaneous Control Module (MCM) MCM_PLAMC field descriptions (continued) Field Description A bus master connection to AXBS input port n is absent A bus master connection to AXBS input port n is present 16.2.3 Platform Control Register (MCM_PLACR) The PLACR register selects the arbitration policy for the crossbar masters and configures the flash memory controller.
Page 252 Memory map/register descriptions Address: F000_3000h base + Ch offset = F000_300Ch ESFC Reset EFDS Reset MCM_PLACR field descriptions Field Description 31–17 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Enable Stalling Flash Controller ESFC Enables stalling flash controller when flash is busy.
Page 253 Chapter 16 Miscellaneous Control Module (MCM) MCM_PLACR field descriptions (continued) Field Description Disable flash data speculation. Enable flash data speculation. Disable Flash Controller Cache DFCC Disables flash controller cache. Enable flash controller cache. Disable flash controller cache. Disable Flash Controller Instruction Caching DFCIC Disables flash controller instruction caching.
Page 254: Compute Operation Control Register (Mcm_Cpo)
Memory map/register descriptions 16.2.4 Compute Operation Control Register (MCM_CPO) This register controls the Compute Operation. Address: F000_3000h base + 40h offset = F000_3040h Reset Reset MCM_CPO field descriptions Field Description 31–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Compute Operation Wake-up on Interrupt CPOWOI No effect.
Page 255 Chapter 16 Miscellaneous Control Module (MCM) MCM_CPO field descriptions (continued) Field Description Request is cleared. Request Compute Operation. KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 256 Memory map/register descriptions KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 257: Crossbar Switch Lite (Axbs-Lite)
Chapter 17 Crossbar Switch Lite (AXBS-Lite) 17.1 Chip-specific AXBS-Lite information 17.1.1 Crossbar-light switch master assignments The masters connected to the crossbar switch are assigned as follows: Master module Master port number ARM core unified bus 17.1.2 Crossbar switch slave assignments This device contains 3 slaves connected to the crossbar switch.
Page 258: Features
Memory Map / Register Definition The crossbar switch connects bus masters and bus slaves using a crossbar switch structure. This structure allows up to four bus masters to access different bus slaves simultaneously, while providing arbitration among the bus masters when they access the same slave.
Page 259: Arbitration
Chapter 17 Crossbar Switch Lite (AXBS-Lite) Because the crossbar switch appears to be just another slave to the master device, the master device has no knowledge of whether it actually owns the slave port it is targeting. While the master does not have control of the slave port it is targeting, it simply waits. After the master has control of the slave port it is targeting, the master remains in control of the slave port until it relinquishes the slave port by running an IDLE cycle or by targeting a different slave port for its next access.
Page 260 Functional Description 17.4.2.2 Fixed-priority operation When operating in fixed-priority mode, each master is assigned a unique priority level with the highest numbered master having the highest priority (for example, in a system with 5 masters, master 1 has lower priority than master 3). If two masters request access to the same slave port, the master with the highest priority gains control over the slave port.
Page 261: Initialization/Application Information
Chapter 17 Crossbar Switch Lite (AXBS-Lite) After granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line is granted access to the slave port at the next transfer boundary, or possibly on the next clock cycle if the current master has no pending access request.
Page 262 Initialization/application information KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 263: Llwu Interrupt
Chapter 18 Low-Leakage Wakeup Unit (LLWU) 18.1 LLWU interrupt The interrupt requests of external sources and internal peripherals are used in wakeup. NOTE Do not mask the LLWU interrupt when in LLS/VLLSx mode. Masking the interrupt prevents the device from exiting stop mode when a wakeup is detected.
Page 264: Introduction
Introduction Table 18-1. Wakeup Source (continued) LLWU pin Module source or pin name LLWU_M0IF LPTMR0 LLWU_M1IF CMP0 LLWU_M2IF Reserved LLWU_M3IF Reserved LLWU_M4IF Reserved LLWU_M5IF RTC Alarm LLWU_M6IF Reserved LLWU_M7IF RTC Seconds 18.2 Introduction The LLWU module allows the user to select up to 16 external pins and up to 8 internal modules as interrupt wake-up sources from low-leakage power modes.
Page 265: Low-Leakage Wakeup Unit (Llwu)
Chapter 18 Low-Leakage Wakeup Unit (LLWU) • Wake-up inputs that are activated after MCU enters a low-leakage power mode • Optional digital filters provided to qualify an external pin detect. Note that when the LPO clock is disabled, the filters are disabled and bypassed. 18.2.2 Modes of operation The LLWU module becomes functional on entry into a low-leakage power mode.
Page 266: Block Diagram
Introduction 18.2.2.4 Debug mode When the chip is in Debug mode and then enters LLS or a VLLSx mode, no debug logic works in the fully-functional low-leakage mode. Upon an exit from the LLS or VLLSx mode, the LLWU becomes inactive. 18.2.3 Block diagram The following figure is the block diagram for the LLWU module.
Page 267: Llwu Signal Descriptions
Chapter 18 Low-Leakage Wakeup Unit (LLWU) 18.3 LLWU signal descriptions The signal properties of LLWU are shown in the table found here. The external wakeup input pins can be enabled to detect either rising-edge, falling-edge, or on any change. Table 18-2. LLWU signal descriptions Signal Description LLWU_Pn...
Page 268: Llwu Pin Enable 1 Register (Llwu_Pe1)
Memory map/register definition LLWU memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_C000 LLWU Pin Enable 1 register (LLWU_PE1) 18.4.1/268 4007_C001 LLWU Pin Enable 2 register (LLWU_PE2) 18.4.2/269 4007_C002 LLWU Pin Enable 3 register (LLWU_PE3) 18.4.3/270 4007_C003 LLWU Pin Enable 4 register (LLWU_PE4) 18.4.4/271...
Page 269: Llwu Pin Enable 2 Register (Llwu_Pe2)
Chapter 18 Low-Leakage Wakeup Unit (LLWU) LLWU_PE1 field descriptions (continued) Field Description External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 3–2 Wakeup Pin Enable For LLWU_P1 WUPE1...
Page 270: Llwu Pin Enable 3 Register (Llwu_Pe3)
Memory map/register definition LLWU_PE2 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 5–4 Wakeup Pin Enable For LLWU_P6 WUPE6 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 271: Llwu Pin Enable 4 Register (Llwu_Pe4)
Chapter 18 Low-Leakage Wakeup Unit (LLWU) LLWU_PE3 field descriptions Field Description 7–6 Wakeup Pin Enable For LLWU_P11 WUPE11 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 5–4...
Page 272: Llwu Module Enable Register (Llwu_Me)
Memory map/register definition Address: 4007_C000h base + 3h offset = 4007_C003h Read WUPE15 WUPE14 WUPE13 WUPE12 Write Reset LLWU_PE4 field descriptions Field Description 7–6 Wakeup Pin Enable For LLWU_P15 WUPE15 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 273 Chapter 18 Low-Leakage Wakeup Unit (LLWU) types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 4h offset = 4007_C004h Read WUME7 WUME6 WUME5 WUME4 WUME3 WUME2 WUME1 WUME0 Write Reset LLWU_ME field descriptions Field...
Page 274: Llwu Flag 1 Register (Llwu_F1)
Memory map/register definition LLWU_ME field descriptions (continued) Field Description Wakeup Module Enable For Module 0 WUME0 Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source 18.4.6 LLWU Flag 1 register (LLWU_F1) LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode.
Page 275 Chapter 18 Low-Leakage Wakeup Unit (LLWU) LLWU_F1 field descriptions (continued) Field Description LLWU_P6 input was not a wakeup source LLWU_P6 input was a wakeup source Wakeup Flag For LLWU_P5 WUF5 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF5.
Page 276: Llwu Flag 2 Register (Llwu_F2)
Memory map/register definition 18.4.7 LLWU Flag 2 register (LLWU_F2) LLWU_F2 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit.
Page 277: Llwu Flag 3 Register (Llwu_F3)
Chapter 18 Low-Leakage Wakeup Unit (LLWU) LLWU_F2 field descriptions (continued) Field Description Wakeup Flag For LLWU_P12 WUF12 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF12. LLWU_P12 input was not a wakeup source LLWU_P12 input was a wakeup source Wakeup Flag For LLWU_P11...
Page 278 Memory map/register definition NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information.
Page 279: Llwu Pin Filter 1 Register (Llwu_Filt1)
Chapter 18 Low-Leakage Wakeup Unit (LLWU) LLWU_F3 field descriptions (continued) Field Description Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Module 2 input was not a wakeup source Module 2 input was a wakeup source Wakeup flag For module 1 MWUF1...
Page 280: Llwu Pin Filter 2 Register (Llwu_Filt2)
Memory map/register definition LLWU_FILT1 field descriptions (continued) Field Description Pin Filter 1 was not a wakeup source Pin Filter 1 was a wakeup source 6–5 Digital Filter On External Pin FILTE Controls the digital filter options for the external pin detect. Filter disabled Filter posedge detect enabled Filter negedge detect enabled...
Page 281: Functional Description
Chapter 18 Low-Leakage Wakeup Unit (LLWU) LLWU_FILT2 field descriptions (continued) Field Description Pin Filter 2 was not a wakeup source Pin Filter 2 was a wakeup source 6–5 Digital Filter On External Pin FILTE Controls the digital filter options for the external pin detect. Filter disabled Filter posedge detect enabled Filter negedge detect enabled...
Page 282: Lls Mode
Functional description For internal module interrupts, the WUMEx bit enables the associated module interrupt as a wakeup source. 18.5.1 LLS mode Wakeup events triggered from either an external pin input or an internal module interrupt, result in a CPU interrupt flow to begin user code execution. 18.5.2 VLLS modes For any wakeup from VLLS, recovery is always via a reset flow and RCM_SRS[WAKEUP] is set indicating the low-leakage mode was active.
Page 283: Peripheral Bridge (Aips-Lite)
Chapter 19 Peripheral Bridge (AIPS-Lite) 19.1 Chip-specific AIPS-Lite information 19.1.1 Number of peripheral bridges This device contains one peripheral bridge. 19.1.2 Memory maps The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map for the memory slot assignment for each module.
Page 284: General Operation
Memory map/register definition 19.2.2 General operation The slave devices connected to the peripheral bridge are modules which contain a programming model of control and status registers. The system masters read and write these registers through the peripheral bridge. The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is allocated one or more 4-KB block(s) of the memory map.
Page 285 Chapter 19 Peripheral Bridge (AIPS-Lite) Address: 0h base + 0h offset = 0h Reset Reset * Notes: • The reset value is chip-dependent and can be found in the chip-specific AIPS information. AIPS_MPRA field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 286: Peripheral Access Control Register (Aips_Pacrn)
Memory map/register definition AIPS_MPRA field descriptions (continued) Field Description This master is not trusted for write accesses. This master is trusted for write accesses. Master 2 Privilege Level MPL2 Specifies how the privilege level of the master is determined. Accesses from this master are forced to user-mode. Accesses from this master are not forced to user-mode.
Page 287 Chapter 19 Peripheral Bridge (AIPS-Lite) Reset * Notes: • The reset value is chip-dependent and can be found in the AIPS chip-specific information. AIPS_PACRn field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses.
Page 288 Memory map/register definition AIPS_PACRn field descriptions (continued) Field Description This peripheral allows write accesses. This peripheral is write protected. Trusted Protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates.
Page 289 Chapter 19 Peripheral Bridge (AIPS-Lite) AIPS_PACRn field descriptions (continued) Field Description This peripheral allows write accesses. This peripheral is write protected. Trusted Protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates.
Page 290 Memory map/register definition AIPS_PACRn field descriptions (continued) Field Description This peripheral allows write accesses. This peripheral is write protected. Trusted Protect Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates.
Page 291: Functional Description
Chapter 19 Peripheral Bridge (AIPS-Lite) AIPS_PACRn field descriptions (continued) Field Description This peripheral allows write accesses. This peripheral is write protected. Trusted Protect Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates.
Page 292 Functional description KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 293: Chip-Specific Dmamux Information
Chapter 20 Direct Memory Access Multiplexer (DMAMUX) 20.1 Chip-specific DMAMUX information 20.1.1 DMA MUX Request Sources This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 4 DMA channels. Because of the mux there is no hard correlation between any of the DMA request sources and a specific DMA channel.
Page 294 Chip-specific DMAMUX information Table 20-1. DMA request sources - MUX 0 (continued) Source Source module Source description Async DMA number capable Transmit SPI0 Receive SPI0 Transmit SPI1 Receive SPI1 Transmit Reserved — Reserved — TPM0 Channel 0 TPM0 Channel 1 TPM0 Channel 2 TPM0...
Page 295: Direct Memory Access Multiplexer (Dmamux)
Chapter 20 Direct Memory Access Multiplexer (DMAMUX) Table 20-1. DMA request sources - MUX 0 (continued) Source Source module Source description Async DMA number capable TPM0 Overflow TPM1 Overflow TPM2 Overflow Reserved — Reserved — Reserved — DMA MUX Always enabled DMA MUX Always enabled DMA MUX...
Page 296: Features
Introduction DMA channel #0 DMAMUX Source #1 DMA channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA channel #n Trigger #z Figure 20-1. DMAMUX block diagram 20.2.2 Features The DMAMUX module provides these features: •...
Page 297: External Signal Description
Chapter 20 Direct Memory Access Multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger.
Page 298: Functional Description
Functional description NOTE Setting multiple CHCFG registers with the same source value will result in unpredictable behavior. This is true, even if a channel is disabled (ENBL==0). Before changing the trigger or source settings, a DMA channel must be disabled via CHCFGn[ENBL]. Address: 4002_1000h base + 0h offset + (1d ×...
Page 299: Dma Channels With Periodic Triggering Capability
Chapter 20 Direct Memory Access Multiplexer (DMAMUX) Functionally, the DMAMUX channels may be divided into two classes: • Channels that implement the normal routing functionality plus periodic triggering capability • Channels that implement only the normal routing functionality 20.5.1 DMA channels with periodic triggering capability Besides the normal routing functionality, the first 2 channels of the DMAMUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames, or packets at fixed intervals without the need for processor...
Page 300 Functional description Source #1 Source #2 Source #3 DMA channel #0 Trigger #1 Source #x DMA channel #m-1 Trigger #m Always #1 Always #y Figure 20-2. DMAMUX triggered channels The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor.
Page 301: Dma Channels With No Triggering Capability
Chapter 20 Direct Memory Access Multiplexer (DMAMUX) Peripheral request Trigger DMA request Figure 20-4. DMAMUX channel triggering: ignored trigger This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations: •...
Page 302: Always-Enabled Dma Sources
Functional description 20.5.3 Always-enabled DMA sources In addition to the peripherals that can be used as DMA sources, there are four additional DMA sources that are always enabled. Unlike the peripheral DMA sources, where the peripheral controls the flow of data during DMA transfers, the sources that are always enabled provide no such "throttling"...
Page 303: Initialization/Application Information
Chapter 20 Direct Memory Access Multiplexer (DMAMUX) In this option, the DMA is configured to transfer the data using both minor and major loops, and the DMA channel MUX does the channel reactivation. For this option, the DMA channel should be enabled and pointing to an "always enabled" source. Note that the reactivation of the channel can be continuous (DMA triggering is disabled) or can use the DMA triggering capability.
Page 304 Initialization/application information 2. Configure channel 1 in the DMA, including enabling the channel. 3. Configure a timer for the desired trigger interval. 4. Write 0xC5 to CHCFG1. The following code example illustrates steps 1 and 4 above: void DMAMUX_Init(uint8_t DMA_CH, uint8_t DMAMUX_SOURCE) DMAMUX_0.CHCFG[DMA_CH].B.SOURCE = DMAMUX_SOURCE;...
Page 305 Chapter 20 Direct Memory Access Multiplexer (DMAMUX) volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" *CHCFG1 = 0x00; *CHCFG1 = 0x85; To disable a source: A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCFG registers.
Page 306 Initialization/application information In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 307: Dma Controller Module
Chapter 21 DMA Controller Module 21.1 Introduction Information found here describes the direct memory access (DMA) controller module. It provides an overview of the module and describes in detail its signals and programming model. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail.
Page 308: Features
Introduction The following figure is a simplified block diagram of the 4-channel DMA controller. DREQ0 DREQ1 DREQ2 DREQ3 DACK1 DACK0 DACK3 DACK2 Channel 0 Channel 1 Channel 2 Channel 3 SAR0 SAR1 SAR2 SAR3 Slave Peripheral Bus DAR0 DAR1 DAR2 DAR3 Interrupts DSR0...
Page 309: Dma Transfer Overview
Chapter 21 DMA Controller Module • Automatic hardware acknowledge/done indicator from each channel • Independent source and destination address registers • Optional modulo addressing and automatic updates of source and destination addresses • Independent transfer sizes for source and destination •...
Page 310: Memory Map/Register Definition
Memory Map/Register Definition Control and Data Memory/ Peripheral Read Write Memory/ Peripheral Control and Data Figure 21-2. Dual-Address Transfer Any operation involving a DMA channel follows the same three steps: 1. Channel initialization—The transfer control descriptor, contained in the channel registers, is loaded with address pointers, a byte-transfer count, and control information using accesses from the slave peripheral bus.
Page 311: Source Address Register (Dma_Sarn)
Chapter 21 DMA Controller Module DMA memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_8100 Source Address Register (DMA_SAR0) 0000_0000h 21.3.1/311 4000_8104 Destination Address Register (DMA_DAR0) 0000_0000h 21.3.2/312 DMA Status Register / Byte Count Register 4000_8108 0000_0000h 21.3.3/313...
Page 312: Destination Address Register (Dma_Darn)
Memory Map/Register Definition DMA_SARn field descriptions Field Description Each SAR contains the byte address used by the DMA controller to read data. The SARn is typically aligned on a 0-modulo-ssize boundary—that is, on the natural alignment of the source data. Restriction: Bits 31-20 of this register must be written with one of only several allowed values.
Page 313: Dma Status Register / Byte Count Register (Dma_Dsr_Bcrn)
Chapter 21 DMA Controller Module DMA_DARn field descriptions (continued) Field Description • 0x000x_xxxx • 0x1FFx_xxxx • 0x200x_xxxx • 0x400x_xxxx After being written with one of the allowed values, bits 31-20 read back as the written value. After being written with any other value, bits 31-20 read back as an indeterminate value. 21.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn) DSR and BCR are two logical registers that occupy one 32-bit address.
Page 314 Memory Map/Register Definition Reset DMA_DSR_BCRn field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Configuration Error Any of the following conditions causes a configuration error: • BCR, SAR, or DAR does not match the requested transfer size. •...
Page 315: Dma Control Register (Dma_Dcrn)
Chapter 21 DMA Controller Module DMA_DSR_BCRn field descriptions (continued) Field Description Set when all DMA controller transactions complete as determined by transfer count, or based on error conditions. When BCR reaches 0, DONE is set when the final transfer completes successfully. DONE can also be used to abort a transfer by resetting the status bits.
Page 316 Memory Map/Register Definition DMA_DCRn field descriptions (continued) Field Description Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition. No interrupt is generated. Interrupt signal is enabled. Enable Peripheral Request CAUTION: Be careful: a collision can occur between START and D_REQ when ERQ is 1. Peripheral request is ignored.
Page 317 Chapter 21 DMA Controller Module DMA_DCRn field descriptions (continued) Field Description 16-bit Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) Destination Increment DINC Controls whether the destination address increments after each successful transfer. No change to the DAR after a successful transfer. The DAR increments by 1, 2, 4 depending upon the size of the transfer.
Page 318 Memory Map/Register Definition DMA_DCRn field descriptions (continued) Field Description boundary depends on the initial destination address (DAR). The base address should be aligned to a 0- modulo-(circular buffer size) boundary. Misaligned buffers are not possible. The boundary is forced to the value determined by the upper address bits in the field selection.
Page 319: Functional Description
Chapter 21 DMA Controller Module DMA_DCRn field descriptions (continued) Field Description DMA Channel 2 DMA Channel 3 LCH2 Link Channel 2 Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set). DMA Channel 0 DMA Channel 1 DMA Channel 2...
Page 320: Channel Initialization And Startup
Functional Description • Cycle-steal mode (DCRn[CS] = 1)—Only one complete transfer from source to destination occurs for each request. If DCRn[ERQ] is set, the request is peripheral initiated. A software-initiated request is enabled by setting DCRn[START]. • Continuous mode (DCRn[CS] = 0)—After a software-initiated or peripheral request, the DMA continuously transfers data until BCRn reaches 0.
Page 321: Dual-Address Data Transfer Mode
Chapter 21 DMA Controller Module • SARn is loaded with the source (read) address. If the transfer is from a peripheral device to memory or to another peripheral, the source address is the location of the peripheral data register. If the transfer is from memory to a peripheral device or to memory, the source address is the starting address of the data block.
Page 322: Advanced Data Transfer Controls: Auto-Alignment
Functional Description 21.4.3 Dual-Address Data Transfer Mode Each channel supports dual-address transfers. Dual-address transfers consist of a source data read and a destination data write. The DMA controller module begins a dual-address transfer sequence after a DMA request. If no error condition exists, DSRn[REQ] is set. •...
Page 323: Termination
Chapter 21 DMA Controller Module Consider this example: • AA equals 1. • SARn equals 0x2000_0001. • BCRn equals 0x00_00F0. • SSIZE equals 00 (32 bits). • DSIZE equals 01 (8 bits). Because SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on destination registers.
Page 324 Functional Description KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 325: Reset Control Module (Rcm)
Chapter 22 Reset Control Module (RCM) 22.1 Introduction Information found here describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. AN4503: Power Management for Kinetis MCUs for further details on using the RCM.
Page 326: System Reset Status Register 0 (Rcm_Srs0)
Reset memory map and register descriptions RCM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_F006 Force Mode Register (RCM_FM) 22.2.5/331 4007_F007 Mode Register (RCM_MR) See section 22.2.6/331 4007_F008 Sticky System Reset Status Register 0 (RCM_SSRS0) 22.2.7/332 4007_F009 Sticky System Reset Status Register 1 (RCM_SSRS1)
Page 327: System Reset Status Register 1 (Rcm_Srs1)
Chapter 22 Reset Control Module (RCM) RCM_SRS0 field descriptions (continued) Field Description Watchdog WDOG Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by disabling the watchdog. Reset not caused by watchdog timeout Reset caused by watchdog timeout 4–3 This field is reserved.
Page 328: Reset Pin Filter Control Register (Rcm_Rpfc)
Reset memory map and register descriptions Address: 4007_F000h base + 1h offset = 4007_F001h Read SACKERR MDM_AP LOCKUP Write Reset RCM_SRS1 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 329: Reset Pin Filter Width Register (Rcm_Rpfw)
Chapter 22 Reset Control Module (RCM) NOTE The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled . Address: 4007_F000h base + 4h offset = 4007_F004h Read RSTFLTSS RSTFLTSRW Write Reset RCM_RPFC field descriptions Field...
Page 330 Reset memory map and register descriptions RCM_RPFW field descriptions Field Description 7–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. RSTFLTSEL Reset Pin Filter Bus Clock Select Selects the reset pin bus clock filter width. 00000 Bus clock filter count is 1 00001...
Page 331: Force Mode Register (Rcm_Fm)
Chapter 22 Reset Control Module (RCM) 22.2.5 Force Mode Register (RCM_FM) NOTE The reset values of the bits in the FORCEROM field are for Chip POR only. They are unaffected by other reset types. Address: 4007_F000h base + 6h offset = 4007_F006h Read FORCEROM Write...
Page 332: Sticky System Reset Status Register 0 (Rcm_Ssrs0)
Reset memory map and register descriptions RCM_MR field descriptions Field Description 7–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 2–1 Boot ROM Configuration BOOTROM Indicates the boot source, the boot source remains set until the next System Reset or software can write logic one to clear the corresponding mode bit.
Page 333: Sticky System Reset Status Register 1 (Rcm_Ssrs1)
Chapter 22 Reset Control Module (RCM) RCM_SSRS0 field descriptions (continued) Field Description Reset not caused by external reset pin Reset caused by external reset pin Sticky Watchdog SWDOG Indicates a reset has been caused by the watchdog timer timing out.This reset source can be blocked by disabling the watchdog.
Page 334 Reset memory map and register descriptions RCM_SSRS1 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Sticky Stop Mode Acknowledge Error Reset SSACKERR Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more...
Page 335: Analog-To-Digital Converter (Adc)
The number of ADC channels present on the device is determined by the pinout of the specific device package and is shown in the following table. Table 23-1. Number of KL27 ADC channels and ADC pins Device Number of ADC Channels Number of ADC Pins Package MKL27Z128VFM4 32QFN MKL27Z256VFM4 32QFN MKL27Z128VFT4 48QFN MKL27Z256VFT4...
Page 336: Adc0 Connections/Channel Assignment
Chip-specific ADC information 23.1.2 DMA Support on ADC Applications may require continuous sampling of the ADC that may have considerable load on the CPU. The ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate. The ADC can trigger the DMA (via DMA req) on conversion completion.
Page 337: Adc Analog Supply And Reference Connections
Chapter 23 Analog-to-Digital Converter (ADC) Table 23-2. ADC0 channel assignment (continued) ADC channel Channel Input signal (SC1n[DIFF]= Input signal (SC1n[DIFF]= (SC1n[ADCH]) 10100 AD20 Reserved Reserved 10101 AD21 Reserved Reserved 10110 AD22 Reserved Reserved 10111 AD23 Reserved 12-bit DAC0 Output/ ADC0_SE23 11000 AD24 Reserved...
Page 338: Introduction
Introduction the optional clock source below minimum ADC clock operating frequency. 23.2 Introduction The 16-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE For the chip specific modes of operation, see the power management information of the device.
Page 339: Block Diagram
Chapter 23 Analog-to-Digital Converter (ADC) • Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-Calibration mode 23.2.2 Block diagram The following figure is the ADC module block diagram. ADHWTSA SC1A Conversion trigger SC1n ADHWTSn control ADTRG ADHWT...
Page 340: Adc Signal Descriptions
ADC signal descriptions 23.3 ADC signal descriptions The ADC module supports up to 4 pairs of differential inputs and up to 24 single-ended inputs. Each differential pair requires two inputs, DADPx and DADMx. The ADC also requires four supply/reference/ground connections. NOTE For the number of channels supported on this device as well as information regarding other chip-specific inputs into the ADC...
Page 341: Analog Channel Inputs (Adx)
Chapter 23 Analog-to-Digital Converter (ADC) 23.3.3 Voltage Reference Select and V are the high and low reference voltages for the ADC module. REFSH REFSL The ADC can be configured to accept one of two voltage reference pairs for V REFSH .
Page 342 Memory map and register definitions ADC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_B000 ADC Status and Control Registers 1 (ADC0_SC1A) 0000_001Fh 23.4.1/343 4003_B004 ADC Status and Control Registers 1 (ADC0_SC1B) 0000_001Fh 23.4.1/343 4003_B008 ADC Configuration Register 1 (ADC0_CFG1)
Page 343: Adc Status And Control Registers 1 (Adcx_Sc1N)
Chapter 23 Analog-to-Digital Converter (ADC) 23.4.1 ADC Status and Control Registers 1 (ADCx_SC1n) SC1A is used for both software and hardware trigger modes of operation. To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one status and control register: one for each conversion. The SC1B–SC1n registers indicate potentially multiple SC1 registers for use only in hardware trigger mode.
Page 344 Memory map and register definitions AIEN DIFF ADCH Reset ADCx_SC1n field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Conversion Complete Flag COCO This is a read-only field that is set each time a conversion is completed when the compare function is disabled, or SC2[ACFE]=0 and the hardware average function is disabled, or SC3[AVGE]=0.
Page 345 Chapter 23 Analog-to-Digital Converter (ADC) ADCx_SC1n field descriptions (continued) Field Description The successive approximation converter subsystem is turned off when the channel select bits are all set, that is, ADCH = 11111. This feature allows explicit disabling of the ADC and isolation of the input channel from all sources.
Page 346: Adc Configuration Register 1 (Adcx_Cfg1)
Memory map and register definitions 23.4.2 ADC Configuration Register 1 (ADCx_CFG1) The configuration Register 1 (CFG1) selects the mode of operation, clock source, clock divide, and configuration for low power or long sample time. Address: 4003_B000h base + 8h offset = 4003_B008h Reset ADIV MODE...
Page 347: Adc Configuration Register 2 (Adcx_Cfg2)
Chapter 23 Analog-to-Digital Converter (ADC) ADCx_CFG1 field descriptions (continued) Field Description Short sample time. Long sample time. 3–2 Conversion mode selection MODE Selects the ADC resolution mode. When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
Page 348: Adc Data Result Register (Adcx_Rn)
Memory map and register definitions ADCx_CFG2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 7–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. ADC Mux Select MUXSEL Changes the ADC mux setting to select between alternate sets of ADC channels.
Page 349 Chapter 23 Analog-to-Digital Converter (ADC) Unused bits in R n are cleared in unsigned right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes. For example, when configured for 10-bit single-ended mode, D[15:10] are cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit, that is, bit 10 extended through bit 15.
Page 350: Compare Value Registers (Adcx_Cvn)
Memory map and register definitions 23.4.5 Compare Value Registers (ADCx_CVn) The Compare Value Registers (CV1 and CV2) contain a compare value used to compare the conversion result when the compare function is enabled, that is, SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in different modes of operation for both bit position definition and value format using unsigned or sign-extended 2's complement.
Page 351: Status And Control Register 2 (Adcx_Sc2)
Chapter 23 Analog-to-Digital Converter (ADC) 23.4.6 Status and Control Register 2 (ADCx_SC2) The status and control register 2 (SC2) contains the conversion active, hardware/software trigger select, compare function, and voltage reference select of the ADC module. Address: 4003_B000h base + 20h offset = 4003_B020h Reset REFSEL Reset...
Page 352 Memory map and register definitions ADCx_SC2 field descriptions (continued) Field Description • Software trigger: When software trigger is selected, a conversion is initiated following a write to SC1A. • Hardware trigger: When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input after a pulse of the ADHWTSn input.
Page 353: Status And Control Register 3 (Adcx_Sc3)
Chapter 23 Analog-to-Digital Converter (ADC) 23.4.7 Status and Control Register 3 (ADCx_SC3) The Status and Control Register 3 (SC3) controls the calibration, continuous convert, and hardware averaging functions of the ADC module. Address: 4003_B000h base + 24h offset = 4003_B024h Reset AVGS Reset...
Page 354: Adc Offset Correction Register (Adcx_Ofs)
Memory map and register definitions ADCx_SC3 field descriptions (continued) Field Description 5–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Continuous Conversion Enable ADCO Enables continuous conversions. One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
Page 355: Adc Plus-Side Gain Register (Adcx_Pg)
Chapter 23 Analog-to-Digital Converter (ADC) ADCx_OFS field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Offset Error Correction Value 23.4.9 ADC Plus-Side Gain Register (ADCx_PG) The Plus-Side Gain Register (PG) contains the gain error correction for the plus-side input in differential mode or the overall conversion in single-ended mode.
Page 356: Adc Plus-Side General Calibration Value Register (Adcx_Clpd)
Memory map and register definitions For more information regarding the calibration procedure, please refer to the Calibration function section. Address: 4003_B000h base + 30h offset = 4003_B030h Reset ADCx_MG field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Minus-Side Gain 23.4.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)
Page 357: Adc Plus-Side General Calibration Value Register (Adcx_Clps)
Chapter 23 Analog-to-Digital Converter (ADC) 23.4.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS) For more information, see CLPD register description. Address: 4003_B000h base + 38h offset = 4003_B038h CLPS Reset ADCx_CLPS field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 358: Adc Plus-Side General Calibration Value Register (Adcx_Clp3)
Memory map and register definitions 23.4.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3) For more information, see CLPD register description. Address: 4003_B000h base + 40h offset = 4003_B040h CLP3 Reset ADCx_CLP3 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 359: Adc Plus-Side General Calibration Value Register (Adcx_Clp1)
Chapter 23 Analog-to-Digital Converter (ADC) 23.4.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1) For more information, see CLPD register description. Address: 4003_B000h base + 48h offset = 4003_B048h CLP1 Reset ADCx_CLP1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 360: Adc Minus-Side General Calibration Value Register (Adcx_Clmd)
Memory map and register definitions 23.4.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD) The Minus-Side General Calibration Value (CLMx) registers contain calibration information that is generated by the calibration function. These registers contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0], CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0].
Page 361: Adc Minus-Side General Calibration Value Register (Adcx_Clm4)
Chapter 23 Analog-to-Digital Converter (ADC) ADCx_CLMS field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLMS Calibration Value Calibration Value 23.4.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4) For more information, see CLMD register description.
Page 362: Adc Minus-Side General Calibration Value Register (Adcx_Clm2)
Memory map and register definitions ADCx_CLM3 field descriptions (continued) Field Description CLM3 Calibration Value Calibration Value 23.4.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2) For more information, see CLMD register description. Address: 4003_B000h base + 64h offset = 4003_B064h CLM2 Reset ADCx_CLM2 field descriptions Field...
Page 363: Adc Minus-Side General Calibration Value Register (Adcx_Clm0)
Chapter 23 Analog-to-Digital Converter (ADC) 23.4.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0) For more information, see CLMD register description. Address: 4003_B000h base + 6Ch offset = 4003_B06Ch CLM0 Reset ADCx_CLM0 field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 364: Clock Select And Divide Control
Functional description The ADC module has the capability of automatically averaging the result of multiple conversions. The hardware average function is enabled by setting SC3[AVGE] and operates in any of the conversion modes and configurations. NOTE For the chip specific modes of operation, see the power management information of this MCU.
Page 365: Voltage Reference Selection
Chapter 23 Analog-to-Digital Converter (ADC) 23.5.2 Voltage reference selection The ADC can be configured to accept one of the two voltage reference pairs as the reference voltage (V and V ) used for conversions. REFSH REFSL Each pair contains a positive reference that must be between the minimum Ref Voltage High and V , and a ground reference that must be at the same potential as V .
Page 366: Conversion Control
Functional description Note Asserting more than one hardware trigger select signal (ADHWTSn) at the same time results in unknown results. To avoid this, select only one hardware trigger select signal (ADHWTSn) prior to the next intended conversion. When the conversion is completed, the result is placed in the Rn registers associated with the ADHWTSn received.
Page 367 Chapter 23 Analog-to-Digital Converter (ADC) • ADHWTSn active selects SC1n. • if neither is active, the off condition is selected Note Selecting more than one ADHWTSn prior to a conversion completion will result in unknown results. To avoid this, select only one ADHWTSn prior to a conversion completion.
Page 368 Functional description 23.5.4.3 Aborting conversions Any conversion in progress is aborted when: • Writing to SC1A while it is actively controlling a conversion, aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0, a write to SC1A initiates a new conversion if SC1A[ADCH] is equal to a value other than all 1s. Writing to any of the SC1B–SC1n registers while that specific SC1B–SC1n register is actively controlling a conversion aborts the current conversion.
Page 369 Chapter 23 Analog-to-Digital Converter (ADC) 23.5.4.5 Sample time and total conversion time For short sample, that is, when CFG1[ADLSMP]=0, there is a 2-cycle adder for first conversion over the base sample time of four ADCK cycles. For high-speed conversions, that is, when CFG2[ADHSC]=1, there is an additional 2-cycle adder on any conversion. The table below summarizes sample times for the possible ADC configurations.
Page 370 Functional description If the bus frequency is less than f , precise sample time for continuous conversions ADCK cannot be guaranteed when short sample is enabled, that is, when CFG1[ADLSMP]=0. The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
Page 371 Chapter 23 Analog-to-Digital Converter (ADC) Table 23-7. Base conversion time (BCT) (continued) Mode Base conversion time (BCT) 16b single-ended 25 ADCK cycles 16b differential 34 ADCK cycles Table 23-8. Long sample time adder (LSTAdder) Long sample time adder CFG1[ADLSMP] CFG2[ADLSTS] (LSTAdder) 0 ADCK cycles 20 ADCK cycles...
Page 372 Functional description The conversion time for a single conversion is calculated by using the Equation 1 on page 370, and the information provided in Table 23-5 through Table 23-9. The table below lists the variables of Equation 1 on page 370.
Page 373 Chapter 23 Analog-to-Digital Converter (ADC) The resulting conversion time is generated using the parameters listed in the preceding table. Therefore, for bus clock equal to 8 MHz and ADCK equal to 1 MHz, the resulting conversion time is 57.625 µs, that is, AverageNum. This results in a total conversion time of 1.844 ms.
Page 374: Automatic Compare Function
Functional description If the compare function is either disabled or evaluates true, after the selected number of conversions are completed, the average conversion result is transferred into the data result registers, Rn, and SC1n[COCO] is set. An ADC interrupt is generated upon the setting of SC1n[COCO] if the respective ADC interrupt is enabled, that is, SC1n[AIEN]=1.
Page 375: Calibration Function
Chapter 23 Analog-to-Digital Converter (ADC) With SC2[ACREN] =1, and if the value of CV1 is less than or equal to the value of CV2, then setting SC2[ACFGT] will select a trigger-if-inside-compare-range inclusive-of- endpoints function. Clearing SC2[ACFGT] will select a trigger-if-outside-compare- range, not-inclusive-of-endpoints function.
Page 376 Functional description application uses the ADC in a wide variety of configurations, the configuration for which the highest accuracy is required should be selected, or multiple calibrations can be done for the different configurations. For best calibration results: • Set hardware averaging to maximum, that is, SC3[AVGE]=1 and SC3[AVGS]=11 for an average of 32 •...
Page 377: User-Defined Offset Function
Chapter 23 Analog-to-Digital Converter (ADC) Overall, the calibration routine may take as many as 14k ADCK cycles and 100 bus cycles, depending on the results and the clock source chosen. For an 8 MHz clock source, this length amounts to about 1.7 ms. To reduce this latency, the calibration values, which are offset, plus-side and minus-side gain, and plus-side and minus-side calibration values, may be stored in flash memory after an initial calibration and recovered prior to the first ADC conversion.
Page 378: Temperature Sensor
Functional description Note There is an effective limit to the values of offset that can be set by the user. If the magnitude of the offset is too high, the results of the conversions will cap off at the limits. The offset calibration function may be employed by the user to remove application offsets or DC bias values.
Page 379: Mcu Wait Mode Operation
Chapter 23 Analog-to-Digital Converter (ADC) In application code, the user reads the temperature sensor channel, calculates V , and TEMP compares to V . If V is greater than V the cold slope value is applied in TEMP25 TEMP TEMP25 the preceding equation.
Page 380: Mcu Low-Power Stop Mode Operation
Functional description 23.5.10.1 Normal Stop mode with ADACK disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the ADC in its Idle state. The contents of the ADC registers, including Rn, are unaffected by Normal Stop mode. After exiting from Normal Stop mode, a software or hardware trigger is required to resume conversions.
Page 381: Initialization Information
Chapter 23 Analog-to-Digital Converter (ADC) 23.6 Initialization information This section gives an example that provides some basic direction on how to initialize and configure the ADC module. The user can configure the module for 16-bit, 12-bit, 10-bit, or 8-bit single-ended resolution or 16-bit, 13-bit, 11-bit, or 9-bit differential resolution, single or continuous conversion, and a polled or interrupt approach, among many other options.
Page 382 Initialization information 23.6.1.2 Pseudo-code example In this example, the ADC module is set up with interrupts enabled to perform a single 10- bit conversion at low-power with a long sample time on input channel 1, where ADCK is derived from the bus clock divided by 1. CFG1 = 0x98 (%10011000) Bit 7 ADLPC...
Page 383: Application Information
Chapter 23 Analog-to-Digital Converter (ADC) Reset Initialize ADC CFG1 = 0x98 SC2 = 0x00 SC1n = 0x41 Check SC1n[COCO]=1? Read Rn to clear SC1n[COCO] Continue Figure 23-2. Initialization flowchart example 23.7 Application information The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an ADC.
Page 384 Application information • V and V available as separate pins—When available on a separate pin, both and V must be connected to the same voltage potential as their corresponding MCU digital supply, V and V , and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package.
Page 385: Sources Of Error
Chapter 23 Analog-to-Digital Converter (ADC) high-frequency characteristics. This capacitor is connected between V and V REFH REFL and must be placed as near as possible to the package pins. Resistance in the path is not recommended because the current causes a voltage drop that could result in conversion errors.
Page 386 Application information CADIN = Internal ADC input capacitance NUMTAU = -ln(LSBERR / 2 LSBERR = value of acceptable sampling error in LSBs N = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode or 16 in 16-bit mode Higher source resistances or higher-accuracy sampling is possible by setting CFG1[ADLSMP] and changing CFG2[ADLSTS] to increase the sample window, or decreasing ADCK frequency to increase sample time.
Page 387 Chapter 23 Analog-to-Digital Converter (ADC) • For software triggered conversions, immediately follow the write to SC1 with a Wait instruction or Stop instruction. • For Normal Stop mode operation, select ADACK as the clock source. Operation in Normal Stop reduces V noise but increases effective conversion time due to stop recovery.
Page 388 Application information For 16-bit conversions, the code transitions only after the full code width is present, so the quantization error is -1 LSB to 0 LSB and the code width of each step is 1 LSB. 23.7.2.5 Linearity errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors, but the system designers must be aware of these errors because they affect overall accuracy: •...
Page 389 Chapter 23 Analog-to-Digital Converter (ADC) This error may be reduced by repeatedly sampling the input and averaging the result. Additionally, the techniques discussed in Noise-induced errors reduces this error. • Non-monotonicity: Non-monotonicity occurs when, except for code jitter, the converter converts to a lower code for a higher input voltage. •...
Page 390 Application information KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 391: Comparator (Cmp)
Chapter 24 Comparator (CMP) 24.1 Chip-specific CMP information 24.1.1 CMP instantiation information The device includes and two 8-input multiplexers for both the inverting and non-inverting inputs of the comparator. Each CMP input channel connects to both muxes. Two of the channels are connected to internal sources, leaving resources to support up to 6 input pins.
Page 392: Cmp External References
Chip-specific CMP information 24.1.2 CMP input connections The following table shows the fixed internal connections to the CMP0. Table 24-1. CMP input connections CMP inputs CMP0 CMP0_IN0 CMP0_IN1 CMP0_IN2 CMP0_IN3 12-bit DAC0 reference/ CMP0_IN4 CMP0_IN5 Bandgap 6-bit DAC0 reference 1. This is the PMC bandgap 1V reference voltage. Prior to using as CMP input, ensure that you enable the bandgap buffer by setting PMC_REGSC[BGBE].
Page 393: Introduction
Chapter 24 Comparator (CMP) • In Time Counter mode with prescaler enabled, the delay is 1/2 Prescaler output period. • In Time Counter mode with prescaler bypassed, the delay is 1/2 Prescaler clock period. The delay between the first signal from LPTMR and the second signal from LPTMR must be greater than the analog comparator initialization delay as defined in the device datasheet.
Page 394: 6-Bit Dac Key Features
Introduction • Sampled • Digitally filtered: • Filter can be bypassed • Can be clocked via scaled bus clock • External hysteresis can be used at the same time that the output filter is used for internal functions • Two software selectable performance levels: •...
Page 395: Cmp Block Diagram
Chapter 24 Comparator (CMP) 24.2.4 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. VRSEL VOSEL[5:0] DACEN DAC output PSEL[2:0] Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Sample input...
Page 396 Introduction 24.2.5 CMP block diagram The following figure shows the block diagram for the CMP module. Internal bus FILT_PER EN,PMODE,HYSCTRL[1:0] COUT IER/F CFR/F FILTER_CNT Window Interrupt Polarity Filter control select control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock COUTA Clock CMPO to...
Page 397: Memory Map/Register Definitions
Chapter 24 Comparator (CMP) 24.3 Memory map/register definitions CMP memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_3000 CMP Control Register 0 (CMP0_CR0) 24.3.1/397 4007_3001 CMP Control Register 1 (CMP0_CR1) 24.3.2/398 4007_3002 CMP Filter Period Register (CMP0_FPR) 24.3.3/399 4007_3003 CMP Status and Control Register (CMP0_SCR)
Page 398: Cmp Control Register 1 (Cmpx_Cr1)
Memory map/register definitions CMPx_CR0 field descriptions (continued) Field Description HYSTCTR Comparator hard block hysteresis control Defines the programmable hysteresis level. The hysteresis values associated with each level are device- specific. See the Data Sheet of the device for the exact values. Level 0 Level 1 Level 2...
Page 399: Cmp Filter Period Register (Cmpx_Fpr)
Chapter 24 Comparator (CMP) CMPx_CR1 field descriptions (continued) Field Description See the electrical specifications table in the device Data Sheet for details. Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. High-Speed (HS) Comparison mode selected.
Page 400: Cmp Status And Control Register (Cmpx_Scr)
Memory map/register definitions 24.3.4 CMP Status and Control Register (CMPx_SCR) Address: 4007_3000h base + 3h offset = 4007_3003h Read COUT DMAEN Write Reset CMPx_SCR field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. DMA Enable Control DMAEN Enables the DMA transfer triggered from the CMP module.
Page 401: Dac Control Register (Cmpx_Daccr)
Chapter 24 Comparator (CMP) CMPx_SCR field descriptions (continued) Field Description Analog Comparator Output COUT Returns the current value of the Analog Comparator output, when read. The field is reset to 0 and will read as CR1[INV] when the Analog Comparator module is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
Page 402: Functional Description
Functional description CMPx_MUXCR field descriptions (continued) Field Description This bit is used to enable to MUX pass through mode. Pass through mode is always available but for some devices this feature must be always disabled due to the lack of package pins. Pass Through Mode is disabled.
Page 403: Cmp Functional Modes
Chapter 24 Comparator (CMP) SCR[IER] and SCR[IEF] are used to select the condition which will cause the CMP module to assert an interrupt to the processor. SCR[CFF] is set on a falling-edge and SCR[CFR] is set on rising-edge of the comparator output. The optionally filtered CMPO can be read directly through SCR[COUT].
Page 404 Functional description Note Filtering and sampling settings must be changed only after setting CR1[SE]=0 and CR0[FILTER_CNT]=0x00. This resets the filter to a known state. 24.4.1.1 Disabled mode (# 1) In Disabled mode, the analog comparator is non-functional and consumes no power. CMPO is 0 in this mode.
Page 405 Chapter 24 Comparator (CMP) The analog comparator block is powered and active. CMPO may be optionally inverted, but is not subject to external sampling or filtering. Both window control and filter blocks are completely bypassed. SCR[COUT] is updated continuously. The path from comparator input pins to output pin is operating in combinational unclocked mode.
Page 406: Power Modes
Functional description 24.4.1.4 Sampled, Filtered mode (#s 4B) In Sampled, Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising edge is detected on the filter block clock input.
Page 407: Startup And Operation
Chapter 24 Comparator (CMP) 24.4.2.2 Stop mode operation Depending on clock restrictions related to the MCU core or core peripherals, the MCU is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin.
Page 408: Low-Pass Filter
Functional description comparator and filter. See the Data Sheets for power-on delays of the comparators. The filter delay is specified in the Low-pass filter. • During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] to reflect an input change or a configuration change to one of the components involved in the data path.
Page 409 Chapter 24 Comparator (CMP) Setting FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process. Note Always switch to this setting prior to making any changes in filter parameters. This resets the filter to a known state. Switching CR0[FILTER_CNT] on the fly without this intermediate step can result in unexpected behavior.
Page 410: Cmp Interrupts
CMP interrupts 24.5 CMP interrupts The CMP module is capable of generating an interrupt on either the rising- or falling- edge of the comparator output, or both. The following table gives the conditions in which the interrupt request is asserted and deasserted.
Page 411: Digital-To-Analog Converter
Chapter 24 Comparator (CMP) When DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by setting SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA transfer request to wake up the system from STOP modes. After the data transfer has finished, system will go back to STOP modes.
Page 412: Dac Resets
DAC resets 24.9.1 Voltage reference source select • V connects to the primary voltage source as supply reference of 64 tap resistor ladder • V connects to an alternate voltage source 24.10 DAC resets This module has a single reset input, corresponding to the chip-wide peripheral reset. 24.11 DAC clocks This module has a single clock input, the bus clock.
Page 413: 12-Bit Digital-To-Analog Converter (Dac)
Chapter 25 12-bit Digital-to-Analog Converter (DAC) 25.1 Introduction The 12-bit digital-to-analog converter (DAC) is a low-power, general-purpose DAC. The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator, op-amps, or ADC. 25.2 Features The features of the DAC module include: •...
Page 414: Memory Map/Register Definition
Memory map/register definition DACREF_1 DACREF_2 DACRFS DACRFS AMP buffer DACEN LPEN DACDAT[11:0] Hardware trigger DACBFWMF & DACBWIEN DACSWTRG Data Buffer DACBFRPTF DACBFEN dac_interrupt & DACBTIEN DACBFUP DACBFRPBF DACBFRP & DACBBIEN DACBFMD DACTRGSE Figure 25-1. DAC block diagram 25.4 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions.
Page 415: Dac Data Low Register (Dacx_Datnl)
Chapter 25 12-bit Digital-to-Analog Converter (DAC) DAC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_F000 DAC Data Low Register (DAC0_DAT0L) 25.4.1/415 4003_F001 DAC Data High Register (DAC0_DAT0H) 25.4.2/415 4003_F002 DAC Data Low Register (DAC0_DAT1L) 25.4.1/415 4003_F003 DAC Data High Register (DAC0_DAT1H)
Page 416: Dac Status Register (Dacx_Sr)
Memory map/register definition DACx_DATnH field descriptions (continued) Field Description When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula. V * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer. 25.4.3 DAC Status Register (DACx_SR) If DMA is enabled, the flags can be cleared automatically by DMA when the DMA request is done.
Page 417: Dac Control Register (Dacx_C0)
Chapter 25 12-bit Digital-to-Analog Converter (DAC) 25.4.4 DAC Control Register (DACx_C0) Address: 4003_F000h base + 21h offset = 4003_F021h Read DACTRGSE DACEN DACRFS LPEN DACBTIEN DACBBIEN Write DACSWTRG Reset DACx_C0 field descriptions Field Description DAC Enable DACEN Starts the Programmable Reference Generator operation. The DAC system is disabled.
Page 418: Dac Control Register 1 (Dacx_C1)
Memory map/register definition 25.4.5 DAC Control Register 1 (DACx_C1) Address: 4003_F000h base + 22h offset = 4003_F022h Read DMAEN DACBFMD DACBFEN Write Reset DACx_C1 field descriptions Field Description DMA Enable Select DMAEN DMA is disabled. DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
Page 419: Functional Description
Chapter 25 12-bit Digital-to-Analog Converter (DAC) DACx_C2 field descriptions (continued) Field Description DAC Buffer Read Pointer DACBFRP In normal mode it keeps the current value of the buffer read pointer. FIFO mode, it is the FIFO read pointer. It is writable in FIFO mode. User can configure it to same address to reset FIFO as empty. 3–1 This field is reserved.
Page 420 Functional description 25.5.1.1 DAC data buffer interrupts There are several interrupts and associated flags that can be configured for the DAC buffer. SR[DACBFRPBF] is set when the DAC buffer read pointer reaches the DAC buffer upper limit, that is, C2[DACBFRP] = C2[DACBFUP]. SR[DACBFRPTF] is set when the DAC read pointer is equal to the start position, 0.
Page 421: Dma Operation
Chapter 25 12-bit Digital-to-Analog Converter (DAC) Table 25-1. Modes of DAC data buffer operation Modes Description be happened when DAC is not enabled for 1st data conversion enable. But FIFO mode need to work at buffer Enabled at DACC1[DACBFEN]. In FIFO mode, the DATA BUF will be organized as FIFO. 25.5.2 DMA operation When DMA is enabled, DMA requests are generated instead of interrupt requests.
Page 422 Functional description KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 423: Voltage Reference (Vrefv1)
Chapter 26 Voltage Reference (VREFV1) 26.1 Introduction The Voltage Reference (VREF) is intended to supply an accurate voltage output that can be trimmed in 0.5 mV steps. The VREF can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC, DAC, or CMP.
Page 424: Overview
Introduction 26.1.1 Overview The Voltage Reference provides a buffered reference voltage for use as an external reference. In addition, the buffered reference is available internally for use with on chip peripherals such as ADCs and DACs. Refer to the chip configuration details for a description of these options.
Page 425: Vref Signal Descriptions
Chapter 26 Voltage Reference (VREFV1) power modes it may be desirable to disable the VREF regulator to minimize current consumption. Note however that the accuracy of the output voltage will be reduced (by as much as several mVs) when the VREF regulator is not used. NOTE The assignment of module modes to core modes is chip- specific.
Page 426: Vref Trim Register (Vref_Trm)
Memory Map and Register Definition 26.2.1 VREF Trim Register (VREF_TRM) This register contains bits that contain the trim data for the Voltage Reference. Address: 4007_4000h base + 0h offset = 4007_4000h Read Reserved CHOPEN TRIM Write Reset * Notes: • x = Undefined at reset.
Page 427: Vref Status And Control Register (Vref_Sc)
Chapter 26 Voltage Reference (VREFV1) 26.2.2 VREF Status and Control Register (VREF_SC) This register contains the control bits used to enable the internal voltage reference and to select the buffer mode to be used. Address: 4007_4000h base + 1h offset = 4007_4001h Read VREFST VREFEN...
Page 428: Functional Description
Functional Description VREF_SC field descriptions (continued) Field Description The module is disabled or not stable. The module is stable. MODE_LV Buffer Mode selection These bits select the buffer modes for the Voltage Reference module. Bandgap on only, for stabilization and startup High power buffer mode enabled Low-power buffer mode enabled Reserved...
Page 429 Chapter 26 Voltage Reference (VREFV1) 26.3.2 Voltage Reference Enabled, SC[VREFEN] = 1 When SC[VREFEN] = 1, the Voltage Reference is enabled, and different modes should be set by the SC[MODE_LV] bits. 26.3.2.1 SC[MODE_LV]=00 The internal VREF bandgap is enabled to generate an accurate 1.2 V output that can be trimmed with the TRM register's TRIM[5:0] bitfield.
Page 430: Internal Voltage Regulator
Internal voltage regulator 26.3.2.3 SC[MODE_LV] = 10 The internal VREF bandgap is on. The low power buffer is enabled to generate a buffered 1.2 V voltage to VREF_OUT. It can also be used as a reference to internal analog peripherals such as an ADC channel or analog comparator input. If this mode is entered from the standby mode (SC[MODE_LV] = 00, SC[VREFEN] = 1) there will be a delay before the buffer output is settled at the final value.
Page 431 Chapter 26 Voltage Reference (VREFV1) (chop oscillator start up time). You must wait this time (Tchop_osc_stup) after the internal bandgap has been enabled to ensure the VREF internal reference voltage has stabilized. When the Voltage Reference is already enabled and stabilized, changing SC[MODE_LV] will not clear SC[VREFST] but there will be some startup time before the output voltage at the VREF_OUT pin has settled.
Page 432 Initialization/Application Information KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 433: Chapter 27 Multipurpose Clock Generator Lite (Mcg_Lite)
Chapter 27 Multipurpose Clock Generator Lite (MCG_Lite) 27.1 Introduction The Multipurpose Clock Generator Lite (MCG_Lite) module provides several clock source options for the MCU. This module contains one 48 MHz and one 8/2 MHz Internal Reference Clock (IRC) sources. The module selects one of IRCs or External Oscillator/Clock (EXT) as the MCU clock sources.
Page 434: Block Diagram
Memory map and register definition 27.1.2 Block diagram The block diagram of MCG_Lite is as follows. MCG_Lite HIRC MCGPCLK TRIMs 48 MHz CLKS HIRCEN TRIMs LIRC LIRC IRCLKEN 8 MHz / Glitchless DIV1 MCGOUTCLK Clock Switcher IREFSTEN 2 MHz IRCS IRCS FCRDIV LIRC_DIV1_CLK...
Page 435: Mcg Control Register 1 (Mcg_C1)
Chapter 27 Multipurpose Clock Generator Lite (MCG_Lite) MCG memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4006_4000 MCG Control Register 1 (MCG_C1) 27.2.1/435 4006_4001 MCG Control Register 2 (MCG_C2) 27.2.2/436 4006_4006 MCG Status Register (MCG_S) 27.2.3/437 4006_4008 MCG Status and Control Register (MCG_SC)
Page 436: Mcg Control Register 2 (Mcg_C2)
Memory map and register definition 27.2.2 MCG Control Register 2 (MCG_C2) Address: 4006_4000h base + 1h offset = 4006_4001h Read RANGE0 HGO0 EREFS0 IRCS Write Reset MCG_C2 field descriptions Field Description 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–4 External Clock Source Frequency Range Select RANGE0...
Page 437: Mcg Status Register (Mcg_S)
Chapter 27 Multipurpose Clock Generator Lite (MCG_Lite) 27.2.3 MCG Status Register (MCG_S) Address: 4006_4000h base + 6h offset = 4006_4006h Read CLKST OSCINIT0 Write Reset MCG_S field descriptions Field Description 7–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 3–2 Clock Mode Status CLKST...
Page 438: Mcg Miscellaneous Control Register (Mcg_Mc)
Memory map and register definition MCG_SC field descriptions (continued) Field Description 3–1 Low-frequency Internal Reference Clock Divider FCRDIV Selects the factor value to divide the LIRC source. Division factor is 1. Division factor is 2. Division factor is 4. Division factor is 8. Division factor is 16.
Page 439: Functional Description
Chapter 27 Multipurpose Clock Generator Lite (MCG_Lite) 27.3 Functional description This section presents the functional details of the MCG_Lite module. 27.3.1 Clock mode switching Different states of the MCG_Lite module are shown in the following figure. The arrows indicate the permitted MCG_Lite mode transitions. Figure 27-2.
Page 440: Lirc Divider 1
Functional description To enter LIRC2M mode from HIRC or EXT mode: 1. Write 0b to MCG_C2[IRCS] to select LIRC 2M. 2. Write 1b to MCG_C1[IRCLKEN] to enable LIRC clock (optional). 3. Write 01b to MCG_C1[CLKS] to select LIRC clock source. 4.
Page 441: Mcg-Lite In Low-Power Mode
Chapter 27 Multipurpose Clock Generator Lite (MCG_Lite) 27.3.5 MCG-Lite in Low-power mode In Stop/VLPS mode, MCG-Lite is inactive, HIRC is disabled, and LIRC is disabled except that both MCG_C1[IREFSTEN] and MCG_C1[IRCLKEN] are set before entering the Stop/VLPS mode. In LLS/VLLS mode, MCG-Lite is power down. In VLPR/VLPW mode, MCG-Lite is in Low-power mode, HIRC is disabled, while LIRC can keep working.
Page 442 Functional description KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 443: Oscillator (Osc)
Chapter 28 Oscillator (OSC) 28.1 Chip-specific OSC information 28.1.1 OSC modes of operation with MCG_Lite and RTC The most common method of controlling the OSC block is through MCG_C1[CLKS] and the fields of MCG_C2 register to configure for crystal or external clock operation. OSC_CR also provides control for enabling the OSC module and configuring internal load capacitors for the EXTAL and XTAL pins.
Page 444: Block Diagram
Block Diagram • Automatic Gain Control (AGC) to optimize power consumption in high frequency ranges 3–8 MHz, 8–32 MHz using low-power mode • High gain option in frequency ranges: 32 kHz, 3–8 MHz, and 8–32 MHz • Voltage and frequency filtering to guarantee clock frequency and stability •...
Page 445: Osc Signal Descriptions
Chapter 28 Oscillator (OSC) EXTAL XTAL OSC_CLK_OUT OSC Clock Enable OSCERCLK ERCLKEN XTL_CLK Range selections Oscillator Circuits Low Power config OSC32KCLK 4096 OSC_EN ERCLKEN EREFSTEN Counter CNT_DONE_4096 Control and Decoding OSC clock selection logic OSCCLK STOP Figure 28-1. OSC Module Block Diagram 28.5 OSC Signal Descriptions The table found here shows the user-accessible signals available for the OSC module.
Page 446 External Crystal / Resonator Connections When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself. In the other oscillator modes, load capacitors (C ) and feedback resistor (R ) are required. The following table shows all possible connections. Table 28-2.
Page 447: External Clock Connections
Chapter 28 Oscillator (OSC) EXTAL XTAL Crystal or Resonator Figure 28-4. Crystal/Ceramic Resonator Connections - Connection 3 28.7 External Clock Connections In external clock mode, the pins can be connected as shown in the figure found here. NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it.
Page 448: Osc Memory Map/Register Definition
OSC Memory Map/Register Definition 28.8.1 OSC Memory Map/Register Definition OSC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 28.8.1.1/ 4006_5000 OSC Control Register (OSC0_CR) 28.8.1.1 OSC Control Register (OSCx_CR) NOTE After OSC is enabled and starts generating the clocks, the configurations such as low power and frequency range, must not be changed.
Page 449: Functional Description
Chapter 28 Oscillator (OSC) OSCx_CR field descriptions (continued) Field Description Configures the oscillator load. Disable the selection. Add 2 pF capacitor to the oscillator load. Oscillator 4 pF Capacitor Load Configure SC4P Configures the oscillator load. Disable the selection. Add 4 pF capacitor to the oscillator load. Oscillator 8 pF Capacitor Load Configure SC8P Configures the oscillator load.
Page 450 Functional Description Oscillator OFF OSCCLK OSC_CLK_OUT = Static not requested OSCCLK requested OSCCLK requested && && Select OSC internal clock Select clock from EXTAL signal Start-Up External Clock Mode Oscillator ON, not yet stable Oscillator ON OSC_CLK_OUT = Static OSC_CLK_OUT = EXTAL CNT_DONE_4096 Stable Oscillator ON, Stable...
Page 451: Osc Module Modes
Chapter 28 Oscillator (OSC) 28.9.1.2 Oscillator startup The OSC enters startup state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized.
Page 452 Functional Description Table 28-3. Oscillator modes (continued) Mode Frequency Range High-frequency mode1, high-gain (3 MHz) up to f (8 MHz) osc_hi_1 osc_hi_1 High-frequency mode1, low-power High-frequency mode2, high-gain (8 MHz) up to f (32 MHz) osc_hi_2 osc_hi_2 High-frequency mode2, low-power NOTE For information about low power modes of operation used in this chip and their alignment with some OSC modes, see the...
Page 453: Counter
Chapter 28 Oscillator (OSC) 28.9.2.3 High-Frequency, High-Gain Mode In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels.
Page 454: Low Power Modes Operation
Low power modes operation 28.11 Low power modes operation When the MCU enters Stop modes, the OSC is functional depending on CR[ERCLKEN] and CR[EREFSETN] bit settings. If both these bits are set, the OSC is in operation. In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If CR[ERCLKEN] and CR[EREFSTEN] are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes.
Page 455: Chip-Specific Tpm Information
Chapter 29 Timer/PWM Module (TPM) 29.1 Chip-specific TPM information The following registers are not available in this device: Table 29-1. TPM register Absolute address Register Instance 4003_901C Channel (n) Status and Control TPM1 (TPM1_C2SC) 4003_9020 Channel (n) Value (TPM1_C2V) TPM1 4003_9024 Channel (n) Status and Control TPM1...
Page 456: Clock Options
Chip-specific TPM information 29.1.1 TPM instantiation information This device contains three low power TPM modules (TPM). All TPM modules in the device are configured only as basic TPM function, do not support quadrature decoder function, and all can be functional in Stop/VLPS mode. The clock source is either external or internal in Stop/VLPS mode.
Page 457: Trigger Options
Chapter 29 Timer/PWM Module (TPM) 29.1.3 Trigger options Each TPM has a selectable external trigger input source controlled by TPMx_CONF[TRGSEL] to use for starting the counter and/or reloading the counter. The options available are shown in the following table. Table 29-3. TPM external trigger options TPMx_CONF[TRGSEL] Selected source 0000...
Page 458: Introduction
Introduction 29.2 Introduction The TPM (Timer/PWM Module) is a 2- to 8-channel timer which supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The counter, compare and capture registers are clocked by an asynchronous clock that can remain enabled in low power modes.
Page 459: Modes Of Operation
Chapter 29 Timer/PWM Module (TPM) • In output compare mode the output signal can be set, cleared, pulsed, or toggled on match • All channels can be configured for edge-aligned PWM mode or center-aligned PWM mode • Support the generation of an interrupt and/or DMA request per channel •...
Page 460: Tpm Signal Descriptions
TPM Signal Descriptions CMOD no clock selected (counter disable) module clock prescaler external clock synchronizer (1, 2, 4, 8, 16, 32, 64 or 128) CPWMS Module counter TOIE timer overflow interrupt Channel 0 MS0B:MS0A ELS0B:ELS0A CH0IE channel 0 interrupt CH0F channel 0 output modes logic input capture...
Page 461: Tpm_Chn - Tpm Channel (N) I/O Pin
Chapter 29 Timer/PWM Module (TPM) 29.3.1 TPM_EXTCLK — TPM External Clock The rising edge of the external input signal is used to increment the TPM counter if selected by CMOD[1:0] bits in the SC register. This input signal must be less than half of the TPM counter clock frequency.
Page 462 Memory Map and Register Definition TPM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_8070 Channel Polarity (TPM0_POL) 0000_0000h 29.4.7/470 4003_8084 Configuration (TPM0_CONF) 0000_0000h 29.4.8/471 4003_9000 Status and Control (TPM1_SC) 0000_0000h 29.4.1/463 4003_9004 Counter (TPM1_CNT) 0000_0000h...
Page 463: Status And Control (Tpmx_Sc)
Chapter 29 Timer/PWM Module (TPM) 29.4.1 Status and Control (TPMx_SC) SC contains the overflow status flag and control bits used to configure the interrupt enable, module configuration and prescaler factor. These controls relate to all channels within this module. Address: Base address + 0h offset Reset TOIE CMOD...
Page 464: Counter (Tpmx_Cnt)
Memory Map and Register Definition TPMx_SC field descriptions (continued) Field Description TPM counter has not overflowed. TPM counter has overflowed. Timer Overflow Interrupt Enable TOIE Enables TPM overflow interrupts. Disable TOF interrupts. Use software polling or DMA request. Enable TOF interrupts. An interrupt is generated when TOF equals one. Center-Aligned PWM Select CPWMS Selects CPWM mode.
Page 465: Modulo (Tpmx_Mod)
Chapter 29 Timer/PWM Module (TPM) Address: Base address + 4h offset COUNT Reset TPMx_CNT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. COUNT Counter value 29.4.3 Modulo (TPMx_MOD) The Modulo register contains the modulo value for the TPM counter.
Page 466: Channel (N) Status And Control (Tpmx_Cnsc)
Memory Map and Register Definition 29.4.4 Channel (n) Status and Control (TPMx_CnSC) CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. When switching from one channel mode to a different channel mode, the channel must first be disabled and this must be acknowledged in the TPM counter clock domain.
Page 467 Chapter 29 Timer/PWM Module (TPM) CHIE MSB MSA ELSB ELSA Reset TPMx_CnSC field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel Flag Set by hardware when an event occurs on the channel. CHF is cleared by writing a 1 to the CHF bit. Writing a 0 to CHF has no effect.
Page 468: Channel (N) Value (Tpmx_Cnv)
Memory Map and Register Definition 29.4.5 Channel (n) Value (TPMx_CnV) These registers contain the captured TPM counter value for the input modes or the match value for the output modes. In input capture mode, any write to a CnV register is ignored. In compare modes, writing to a CnV register latches the value into a buffer.
Page 469 Chapter 29 Timer/PWM Module (TPM) Address: Base address + 50h offset Reset Reset TPMx_STATUS field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Timer Overflow Flag See register description TPM counter has not overflowed.
Page 470: Channel Polarity (Tpmx_Pol)
Memory Map and Register Definition TPMx_STATUS field descriptions (continued) Field Description Channel 2 Flag CH2F See the register description. No channel event has occurred. A channel event has occurred. Channel 1 Flag CH1F See the register description. No channel event has occurred. A channel event has occurred.
Page 471: Configuration (Tpmx_Conf)
Chapter 29 Timer/PWM Module (TPM) TPMx_POL field descriptions (continued) Field Description Channel 3 Polarity POL3 The channel polarity is active high. The channel polarity is active low. Channel 2 Polarity POL2 The channel polarity is active high. The channel polarity is active low. Channel 1 Polarity POL1 The channel polarity is active high.
Page 472 Memory Map and Register Definition TPMx_CONF field descriptions (continued) Field Description 27–24 Trigger Select TRGSEL Selects the input trigger to use for starting, reloading and/or pausing the counter. The source of the trigger (external or internal to the TPM) is configured by the TRGSRC field. This field should only be changed when the TPM counter is disabled.
Page 473 Chapter 29 Timer/PWM Module (TPM) TPMx_CONF field descriptions (continued) Field Description When set, the TPM counter will reload with 0 (and initialize PWM outputs to their default value) when a rising edge is detected on the selected trigger input. The trigger input is ignored if the TPM counter is paused during debug mode or doze mode. This field should only be changed when the TPM counter is disabled.
Page 474: Functional Description
Functional description TPMx_CONF field descriptions (continued) Field Description TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. TPM counter continues in debug mode. Doze Enable DOZEEN Configures the TPM behavior in wait mode. Internal TPM counter continues in Doze mode.
Page 475: Prescaler
Chapter 29 Timer/PWM Module (TPM) The external clock input passes through a synchronizer clocked by the TPM counter clock to assure that counter transitions are properly aligned to counter clock transitions. Therefore, to meet Nyquist criteria considering also jitter, the frequency of the external clock source must be less than half of the counter clock frequency.
Page 476 Functional description The TPM period when using up counting is (MOD + 0x0001) × period of the TPM counter clock. The TOF bit is set when the TPM counter changes from MOD to zero. MOD = 0x0004 timer module counter TOF bit set TOF bit set TOF bit...
Page 477 Chapter 29 Timer/PWM Module (TPM) MOD = 0x0004 Timer module counter TOF bit set TOF bit set TOF bit period of timer module counter clock period of counting = 2 x MOD x period of timer module counter clock Figure 29-4. Example of up-down counting 29.5.3.3 Counter Reset Any write to CNT resets the TPM counter and the channel outputs to their initial values (except for channels in output compare mode).
Page 478: Input Capture Mode
Functional description • When (CSOT = 1), the counter will not start incrementing until a rising edge is detected on the trigger input. • When (CSOO= 1), the counter will stop incrementing whenever the TOF flag is set. The counter does not increment again unless it is disabled, or if CSOT = 1 and a rising edge is detected on the trigger input.
Page 479: Output Compare Mode
Chapter 29 Timer/PWM Module (TPM) was rising edge selected? channel (n) interrupt CHnIE CHnF synchronizer rising edge channel (n) input edge detector timer module clock falling edge was falling edge selected? timer module counter Figure 29-5. Input capture mode The CHnF bit is set on the third rising edge of the counter clock after a valid edge occurs on the channel input.
Page 480: Edge-Aligned Pwm (Epwm) Mode
Functional description MOD = 0x0005 CnV = 0x0003 channel (n) counter channel (n) counter counter overflow match overflow match overflow channel (n) output previous value CHnF bit previous value TOF bit Figure 29-6. Example of the output compare mode when the match toggles the channel output MOD = 0x0005 CnV = 0x0003...
Page 481 Chapter 29 Timer/PWM Module (TPM) The EPWM period is determined by (MOD + 0x0001) and the pulse width (duty cycle) is determined by CnV. The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (TPM counter = CnV), that is, at the end of the pulse width.
Page 482: Center-Aligned Pwm (Cpwm) Mode
Functional description MOD = 0x0008 CnV = 0x0005 counter channel (n) counter overflow match overflow channel (n) output previous value CHnF bit TOF bit Figure 29-11. EPWM signal with ELSnB:ELSnA = X:1 If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal. If (CnV >...
Page 483 Chapter 29 Timer/PWM Module (TPM) timer module counter = 0 channel (n) match channel (n) match counter overflow counter overflow (timer module counting (timer module counting timer module counter = timer module counter = is down) is up) channel (n) output pulse width (2 x CnV) period...
Page 484: Registers Updated From Write Buffers
Functional description If (CnV = 0x0000) then the channel (n) output is a 0% duty cycle CPWM signal. If (CnV > MOD), then the channel (n) output is a 100% duty cycle CPWM signal, although the CHnF bit is set when the counter changes from incrementing to decrementing.
Page 485: Dma
Chapter 29 Timer/PWM Module (TPM) 29.5.9 DMA The channel and overflow flags generate a DMA transfer request according to DMA and CHnIE/TOIE bits. See the following table for more information. Table 29-6. DMA Transfer Request CHnIE/ Channel/Overflow DMA Transfer Request Channel/Overflow Interrupt TOIE The channel/overflow DMA transfer request is...
Page 486: Reset Overview
Functional description 29.5.11 Reset Overview The TPM is reset whenever any chip reset occurs. When the TPM exits from reset: • the TPM counter and the prescaler counter are zero and are stopped (CMOD[1:0] = 0:0); • the timer overflow interrupt is zero; •...
Page 487: Chip-Specific Pit Information
Chapter 30 Periodic Interrupt Timer (PIT) 30.1 Chip-specific PIT information 30.1.1 PIT/DMA periodic trigger assignments The PIT generates periodic trigger events to the DMA channel mux as shown in this table. Table 30-1. PIT channel assignments for periodic DMA triggering PIT channel DMA channel number PIT Channel 0...
Page 488: Introduction
Introduction 30.1.4 PIT/DAC triggers PIT Channel 0 is configured as the DAC hardware trigger source. For more details, see chapter. 30.2 Introduction The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels.
Page 489: Signal Description
Chapter 30 Periodic Interrupt Timer (PIT) 30.2.2 Features The main features of this block are: • Ability of timers to generate DMA trigger pulses • Ability of timers to generate interrupts • Maskable interrupts • Independent timeout periods for each timer 30.3 Signal description The PIT module has no external pins.
Page 490: Pit Module Control Register (Pit_Mcr)
Memory map/register description 30.4.1 PIT Module Control Register (PIT_MCR) This register enables or disables the PIT timer clocks and controls the timers when the PIT enters the Debug mode. Access: User read/write Address: 4003_7000h base + 0h offset = 4003_7000h Reset MDIS Reset...
Page 491: Pit Upper Lifetime Timer Register (Pit_Ltmr64H)
Chapter 30 Periodic Interrupt Timer (PIT) PIT_MCR field descriptions (continued) Field Description Freeze Allows the timers to be stopped when the device enters the Debug mode. Timers continue to run in Debug mode. Timers are stopped in Debug mode. 30.4.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H) This register is intended for applications that chain timer 0 and timer 1 to build a 64-bit lifetimer.
Page 492: Timer Load Value Register (Pit_Ldvaln)
Memory map/register description Address: 4003_7000h base + E4h offset = 4003_70E4h Reset PIT_LTMR64L field descriptions Field Description Life Timer value Shows the value of timer 0 at the time LTMR64H was last read. It will only update if LTMR64H is read. 30.4.4 Timer Load Value Register (PIT_LDVALn) These registers select the timeout period for the timer interrupts.
Page 493: Timer Control Register (Pit_Tctrln)
Chapter 30 Periodic Interrupt Timer (PIT) PIT_CVALn field descriptions Field Description Current Timer Value Represents the current timer value, if the timer is enabled. NOTE: • If the timer is disabled, do not use this field as its value is unreliable. •...
Page 494: Timer Flag Register (Pit_Tflgn)
Functional description PIT_TCTRLn field descriptions (continued) Field Description Timer n is disabled. Timer n is enabled. 30.4.7 Timer Flag Register (PIT_TFLGn) These registers hold the PIT interrupt flags. Access: User read/write Address: 4003_7000h base + 10Ch offset + (16d × i), where i=0d to 1d Reset Reset PIT_TFLGn field descriptions...
Page 495: General Operation
Chapter 30 Periodic Interrupt Timer (PIT) 30.5.1 General operation This section gives detailed information on the internal operation of the module. Each timer can be used to generate trigger pulses and interrupts. Each interrupt is available on a separate interrupt line. 30.5.1.1 Timers The timers generate triggers at periodic intervals, when enabled.
Page 496: Interrupts
Initialization and application information Timer enabled New start Value p2 set Start value = p1 Trigger event Figure 30-4. Dynamically setting a new load value 30.5.1.2 Debug mode In Debug mode, the timers will be frozen based on MCR[FRZ]. This is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system, for example, the timer values, and then continue the operation.
Page 497: Example Configuration For Chained Timers
Chapter 30 Periodic Interrupt Timer (PIT) • Timer 1 creates an interrupt every 5.12 ms. • Timer 3 creates a trigger event every 30 ms. The PIT module must be activated by writing a 0 to MCR[MDIS]. The 50 MHz clock frequency equates to a clock period of 20 ns. Timer 1 needs to trigger every 5.12 ms/20 ns = 256,000 cycles and Timer 3 every 30 ms/20 ns = 1,500,000 cycles.
Page 498: Example Configuration For The Lifetime Timer
Example configuration for the lifetime timer The 100 MHz clock frequency equates to a clock period of 10 ns, so the PIT needs to count for 6000 million cycles, which is more than a single timer can do. So, Timer 1 is set up to trigger every 6 s (600 million cycles).
Page 499 Chapter 30 Periodic Interrupt Timer (PIT) PIT_LDVAL0 = 0xFFFFFFFF; // setup timer 0 for maximum counting period PIT_TCTRL0 = TEN; // start timer 0 To access the lifetime, read first LTMR64H and then LTMR64L. current_uptime = PIT_LTMR64H<<32; current_uptime = current_uptime + PIT_LTMR64L; KL27 Sub-Family Reference Manual , Rev.
Page 500 Example configuration for the lifetime timer KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 501: Low-Power Timer (Lptmr)
Chapter 31 Low-Power Timer (LPTMR) 31.1 Chip-specific LPTMR information 31.1.1 LPTMR instantiation information The low-power timer (LPTMR) allows operation during all power modes. The LPTMR can operate as a real-time interrupt or pulse accumulator. It includes a 2 prescaler (real- time interrupt mode) or glitch filter (pulse accumulator mode).
Page 502: Introduction
Introduction 31.1.3 LPTMR prescaler/glitch filter clocking options The prescaler and glitch filter of the LPTMR module can be clocked from one of four sources determined by LPTMR0_PSR[PCS]. The following table shows the chip-specific clock assignments for this field. NOTE The chosen clock must remain enabled if the LPTMR is to continue operating in all required low-power modes.
Page 503: Modes Of Operation
Chapter 31 Low-Power Timer (LPTMR) 31.2.2 Modes of operation The following table describes the operation of the LPTMR module in various modes. Table 31-1. Modes of operation Modes Description The LPTMR operates normally. The LPTMR continues to operate normally and Wait may be configured to exit the low-power mode by generating an interrupt request.
Page 504: Memory Map And Register Definition
Memory map and register definition 31.4 Memory map and register definition LPTMR memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_0000 Low Power Timer Control Status Register (LPTMR0_CSR) 0000_0000h 31.4.1/504 4004_0004 Low Power Timer Prescale Register (LPTMR0_PSR) 0000_0000h 31.4.2/505 4004_0008...
Page 505: Low Power Timer Prescale Register (Lptmrx_Psr)
Chapter 31 Low-Power Timer (LPTMR) LPTMRx_CSR field descriptions (continued) Field Description Configures the input source to be used in Pulse Counter mode. TPS must be altered only when the LPTMR is disabled. The input connections vary by device. See the for information on the connections to these inputs.
Page 506 Memory map and register definition LPTMRx_PSR field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–3 Prescale Value PRESCALE Configures the size of the Prescaler in Time Counter mode or width of the glitch filter in Pulse Counter mode.
Page 507: Low Power Timer Compare Register (Lptmrx_Cmr)
Chapter 31 Low-Power Timer (LPTMR) LPTMRx_PSR field descriptions (continued) Field Description Prescaler/glitch filter clock 0 selected. Prescaler/glitch filter clock 1 selected. Prescaler/glitch filter clock 2 selected. Prescaler/glitch filter clock 3 selected. 31.4.3 Low Power Timer Compare Register (LPTMRx_CMR) Address: 4004_0000h base + 8h offset = 4004_0008h COMPARE Reset LPTMRx_CMR field descriptions...
Page 508: Functional Description
Functional description LPTMRx_CNR field descriptions (continued) Field Description COUNTER Counter Value The CNR returns the value of the LPTMR counter at the time this register was last written. Writing the CNR will latch the current value of the LPTMR for subsequent reading, the value written is ignored. 31.5 Functional description 31.5.1 LPTMR power and reset The LPTMR remains powered in all power modes, including low-leakage modes.
Page 509: Lptmr Prescaler/Glitch Filter
Chapter 31 Low-Power Timer (LPTMR) 31.5.3 LPTMR prescaler/glitch filter The LPTMR prescaler and glitch filter share the same logic which operates as a prescaler in Time Counter mode and as a glitch filter in Pulse Counter mode. NOTE The prescaler/glitch filter configuration must not be altered when the LPTMR is enabled.
Page 510: Lptmr Compare
Functional description The CNR will increment each time the glitch filter output asserts. In Pulse Counter mode, the maximum rate at which the CNR can increment is once every 2 to 2 prescaler clock edges. When first enabled, the glitch filter will wait an additional one or two prescaler clock edges due to synchronization logic.
Page 511: Lptmr Hardware Trigger
Chapter 31 Low-Power Timer (LPTMR) The CNR cannot be initialized, but can be read at any time. On each read of the CNR, software must first write to the CNR with any value. This will synchronize and register the current value of the CNR into a temporary register. The contents of the temporary register are returned on each read of the CNR.
Page 512 Functional description KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 513: Real Time Clock (Rtc)
Chapter 32 Real Time Clock (RTC) 32.1 Chip-specific RTC information 32.1.1 RTC Instantiation Information RTC prescaler is clocked by ERCLK32K. RTC is reset on POR Only. RTC_CR[OSCE] can override the configuration of the System OSC, configuring the OSC for 32 kHz crystal operation in all power modes except VLLS0, and through any System Reset.
Page 514: Features
Register definition 32.2.1 Features The RTC module features include: • 32-bit seconds counter with roll-over protection and 32-bit alarm • 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm • Register write protection • Lock register requires POR or software reset to enable write access •...
Page 515: Rtc Time Seconds Register (Rtc_Tsr)
Chapter 32 Real Time Clock (RTC) Writing to a register protected by the lock register does not generate a bus error, but the write will not complete. RTC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_D000 RTC Time Seconds Register (RTC_TSR)
Page 516: Rtc Time Alarm Register (Rtc_Tar)
Register definition RTC_TPR field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Time Prescaler Register When the time counter is enabled, the TPR is read only and increments every 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or SR[TIF] are set.
Page 517 Chapter 32 Real Time Clock (RTC) RTC_TCR field descriptions (continued) Field Description Current value used by the compensation logic for the present second interval. Updated once a second if the CIC equals 0 with the contents of the TCR field. If the CIC does not equal zero then it is loaded with zero (compensation is not enabled for that second increment).
Page 518: Rtc Control Register (Rtc_Cr)
Register definition 32.3.5 RTC Control Register (RTC_CR) Address: 4003_D000h base + 10h offset = 4003_D010h Reset SC2P SC4P SC8P WPE SWR Reset RTC_CR field descriptions Field Description 31–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 23–15 This field is reserved.
Page 519 Chapter 32 Real Time Clock (RTC) RTC_CR field descriptions (continued) Field Description Oscillator 8pF Load Configure SC8P Disable the load. Enable the additional load. Oscillator 16pF Load Configure SC16P Disable the load. Enable the additional load. Clock Output CLKO The 32 kHz clock is output to other peripherals. The 32 kHz clock is not output to other peripherals.
Page 520: Rtc Status Register (Rtc_Sr)
Register definition 32.3.6 RTC Status Register (RTC_SR) Address: 4003_D000h base + 14h offset = 4003_D014h Reset Reset RTC_SR field descriptions Field Description 31–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Time Counter Enable When time counter is disabled the TSR register and TPR register are writeable, but do not increment.
Page 521: Rtc Lock Register (Rtc_Lr)
Chapter 32 Real Time Clock (RTC) 32.3.7 RTC Lock Register (RTC_LR) Address: 4003_D000h base + 18h offset = 4003_D018h Reset Reset RTC_LR field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 522: Rtc Interrupt Enable Register (Rtc_Ier)
Register definition 32.3.8 RTC Interrupt Enable Register (RTC_IER) Address: 4003_D000h base + 1Ch offset = 4003_D01Ch Reset Reserved TSIE TAIE TOIE TIIE Reset RTC_IER field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–8 This field is reserved.
Page 523: Functional Description
Chapter 32 Real Time Clock (RTC) RTC_IER field descriptions (continued) Field Description Time overflow flag does not generate an interrupt. Time overflow flag does generate an interrupt. Time Invalid Interrupt Enable TIIE Time invalid flag does not generate an interrupt. Time invalid flag does generate an interrupt.
Page 524: Time Counter
Functional description 32.4.1.3 Supervisor access When the supervisor access control bit is clear, only supervisor mode software can write to the RTC registers, non-supervisor mode software will generate a bus error. Both supervisor and non-supervisor mode software can always read the RTC registers. 32.4.2 Time counter The time counter consists of a 32-bit seconds counter that increments once every second and a 16-bit prescaler register that increments once every 32.768 kHz clock cycle.
Page 525: Time Alarm
Chapter 32 Real Time Clock (RTC) register. The RTC itself does not calculate the amount of compensation that is required, although the 1 Hz clock is output to an external pin in support of external calibration logic. Crystal compensation can be supported by using firmware and crystal characteristics to determine the compensation amount.
Page 526: Update Mode
Functional description 32.4.5 Update mode The Update Mode field in the Control register (CR[UM]) configures software write access to the Time Counter Enable (SR[TCE]) field. When CR[UM] is clear, SR[TCE] can be written only when LR[SRL] is set. When CR[UM] is set, SR[TCE] can also be written when SR[TCE] is clear or when SR[TIF] or SR[TOF] are set.
Page 527: Universal Serial Bus (Usb) Fs Subsystem
Chapter 33 Universal Serial Bus (USB) FS Subsystem 33.1 Chip-specific USBFS information 33.1.1 Universal Serial Bus (USB) FS Subsystem The USB FS subsystem includes these components: • Dual-role USB controller that supports a full-speed (FS) device . The module complies with the USB 2.0 specification. •...
Page 528: Usb Power Distribution
Chip-specific USBFS information Waking from a low power mode (except in LLS/VLLS mode where USB is not powered) occurs through an asynchronous interrupt triggered by activity on the USB bus. Setting the USBTRC0[USBRESMEN] bit enables this function. 33.1.3 USB Power Distribution This chip includes an internal 5 V to 3.3 V USB regulator that powers the USB transceiver or the MCU (depending on the application).
Page 529 Chapter 33 Universal Serial Bus (USB) FS Subsystem 33.1.3.2 Li-Ion battery power supply The chip can also be powered by a single Li-ion battery. In this case, VOUT33 is connected to VDD. The USB regulator must be enabled by default to power the MCU. When connected to a USB host, the input source of this regulator is switched to the USB bus supply from the Li-ion battery.
Page 530: Usb Power Management
Introduction To PMC and Pads VOUT33 Cstab Chip TYPE A VREGIN VBUS Regulator USB0_DP XCVR USB0_DM Controller Figure 33-4. USB regulator bus supply 33.1.4 USB power management The regulator should be put into STANDBY mode whenever the chip is in Stop mode. 33.2 Introduction This chapter describes the USB full speed controller.
Page 531: Usb
Chapter 33 Universal Serial Bus (USB) FS Subsystem • Errata for “USB Revision 2.0 April 27, 2000” as of 12/7/2000 • Errata for “USB Revision 2.0 April 27, 2000” as of 12/7/2000 • Pull-up / Pull-down Resistors (USB Engineering Change Notice) •...
Page 532: Usbfs Features
Functional description For additional information, see the USB 2.0 specification. Host PC External Hub External Hub USB Cable Root Host Software USB Cable USB Cable USB Cables USB Peripherals Figure 33-5. Example USB 2.0 system configuration 33.2.3 USBFS Features • USB 1.1 and 2.0 compatible FS device controller •...
Page 533: On-Chip Transceiver Required External Components
Chapter 33 Universal Serial Bus (USB) FS Subsystem 33.3.2 On-chip transceiver required external components USB system operation requires external components to ensure that driver output impedance, eye diagram, and VBUS cable fault tolerance requirements are met. DM and DP I/O pads must connect through series resistors (approximately 33 Ω each) to the USB connector on the application printed circuit board (PCB).
Page 534: Programmers Interface
Programmers interface External 5v to 3.3v regulator 3.3v USB_VDD VBUS 33 Ω USB_DM 33 Ω USB_DP Place resistors close to the processor USB connecttor Figure 33-6. Typical Device-only block diagram (bus-powered with external regulator) 33.4 Programmers interface This section discusses the major components of the programming model for the USB module.
Page 535: Usb Data Transfers-Receive (Rx) And Transmit (Tx)
Chapter 33 Universal Serial Bus (USB) FS Subsystem the BDT and buffers in system memory. A semaphore, the OWN bit, is cleared to 0 when the BD entry is owned by the microprocessor. The microprocessor is allowed read and write access to the BD entry and the buffer in system memory when the OWN bit is 0. When the OWN bit is set to 1, the BD entry and the buffer in system memory are owned by USBFS.
Page 536: Addressing Bdt Entries
Programmers interface 33.4.3 Addressing BDT entries An understanding of the addressing mechanism of the Buffer Descriptor Table is useful when accessing endpoint data via USBFS or microprocessor. Some points of interest are: • The BDT occupies up to 512 bytes of system memory. •...
Page 537 Chapter 33 Universal Serial Bus (USB) FS Subsystem The USBFS Controller uses the data stored in the BDs to determine: • Who owns the buffer in system memory • Data0 or Data1 PID • Whether to release ownership upon packet completion •...
Page 538 Programmers interface Table 33-5. Buffer descriptor fields (continued) Field Description Determines whether the processor or USBFS currently owns the buffer. Except when KEEP=1, the SIE hands ownership back to the processor after completing the token by clearing this bit. This must always be the last byte of the BD that the processor updates when it initializes a BD. 0 The processor has access to the BD.
Page 539: Usb Transaction
Chapter 33 Universal Serial Bus (USB) FS Subsystem Table 33-5. Buffer descriptor fields (continued) Field Description Setting BDT_STALL also causes the corresponding USB_ENDPTn[EPSTALL] bit to set. This causes USBOTG to issue a STALL handshake for both directions of the associated endpoint. To clear the stall condition: 1.
Page 540 Programmers interface USB RST SOF Interrupt Generated USB_RST Interrupt Generated SETUP TOKEN DATA TOK_DNE Interrupt Generated DATA IN TOKEN TOK_DNE Interrupt Generated DATA OUT TOKEN TOK_DNE USB Host Function Interrupt Generated Figure 33-8. USB token transaction The USB has two sources for the DMA overrun error: Memory Latency The memory latency may be too high and cause the receive FIFO to overflow.
Page 541: Memory Map/Register Definitions
Chapter 33 Universal Serial Bus (USB) FS Subsystem Table 33-6. USB responses to DMA overrun errors (continued) Errors due to Memory Latency Errors due to Oversized Packets • For host mode, the TOKDNE interrupt is generated and The packet length field written back to the BDT is the the TOK_PID field of the BDT is 1111 to indicate the MaxPacket value that represents the length of the clipped DMA latency error.
Page 542 Memory map/Register definitions USB memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 33.5.16/ 4007_20B4 BDT Page Register 3 (USB0_BDTPAGE3) 33.5.17/ 4007_20C0 Endpoint Control register (USB0_ENDPT0) 33.5.17/ 4007_20C4 Endpoint Control register (USB0_ENDPT1) 33.5.17/ 4007_20C8 Endpoint Control register (USB0_ENDPT2) 33.5.17/ 4007_20CC Endpoint Control register (USB0_ENDPT3)
Page 543: Peripheral Id Register (Usbx_Perid)
Chapter 33 Universal Serial Bus (USB) FS Subsystem USB memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) USB Clock recovery control 33.5.23/ 4007_2140 (USB0_CLK_RECOVER_CTRL) IRC48M oscillator enable register 33.5.24/ 4007_2144 (USB0_CLK_RECOVER_IRC_EN) Clock recovery combined interrupt enable 33.5.25/ 4007_2154 (USB0_CLK_RECOVER_INT_EN)
Page 544: Peripheral Revision Register (Usbx_Rev)
Memory map/Register definitions USBx_IDCOMP field descriptions Field Description 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 1. Ones' complement of PERID[ID]. bits. 33.5.3 Peripheral Revision register (USBx_REV) Contains the revision number of the USB module. Address: 4007_2000h base + 8h offset = 4007_2008h Read Write...
Page 545: Interrupt Status Register (Usbx_Istat)
Chapter 33 Universal Serial Bus (USB) FS Subsystem USBx_ADDINFO field descriptions (continued) Field Description This bit is set if host mode is enabled. IEHOST 33.5.5 Interrupt Status register (USBx_ISTAT) Contains fields for each of the interrupt sources within the USB Module. Each of these fields are qualified with their respective interrupt enable bits.
Page 546: Interrupt Enable Register (Usbx_Inten)
Memory map/Register definitions 33.5.6 Interrupt Enable register (USBx_INTEN) Contains enable fields for each of the interrupt sources within the USB Module. Setting any of these bits enables the respective interrupt source in the ISTAT register. This register contains the value of 0x00 after a reset. Address: 4007_2000h base + 84h offset = 4007_2084h Read STALLEN...
Page 547: Error Interrupt Status Register (Usbx_Errstat)
Chapter 33 Universal Serial Bus (USB) FS Subsystem 33.5.7 Error Interrupt Status register (USBx_ERRSTAT) Contains enable bits for each of the error sources within the USB Module. Each of these bits are qualified with their respective error enable bits. All bits of this register are logically OR'd together and the result placed in the ERROR bit of the ISTAT register.
Page 548: Error Interrupt Enable Register (Usbx_Erren)
Memory map/Register definitions 33.5.8 Error Interrupt Enable register (USBx_ERREN) Contains enable bits for each of the error interrupt sources within the USB module. Setting any of these bits enables the respective interrupt source in ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore, the interrupt does not typically correspond with the end of a token being processed.
Page 549: Status Register (Usbx_Stat)
Chapter 33 Universal Serial Bus (USB) FS Subsystem 33.5.9 Status register (USBx_STAT) Reports the transaction status within the USB module. When the processor's interrupt controller has received a TOKDNE, interrupt the Status Register must be read to determine the status of the previous endpoint communication. The data in the status register is valid when TOKDNE interrupt is asserted.
Page 550: Control Register (Usbx_Ctl)
Memory map/Register definitions 33.5.10 Control register (USBx_CTL) Provides various control and configuration information for the USB module. Address: 4007_2000h base + 94h offset = 4007_2094h Read TXSUSPENDTOKENB JSTATE Write Reset Read ODDRST USBENSOFEN Write Reset USBx_CTL field descriptions Field Description Live USB differential receiver JSTATE signal JSTATE The polarity of this signal is affected by the current state of LSEN .
Page 551: Address Register (Usbx_Addr)
Chapter 33 Universal Serial Bus (USB) FS Subsystem 33.5.11 Address register (USBx_ADDR) Holds the unique USB address that the USB module decodes when in Peripheral mode (HOSTMODEEN=0). CTL[USBENSOFEN] must be 1. The Address register is reset to 0x00 after the reset input becomes active or the USB module decodes a USB reset signal. This action initializes the Address register to decode address 0x00 as required by the USB specification.
Page 552: Frame Number Register Low (Usbx_Frmnuml)
Memory map/Register definitions USBx_BDTPAGE1 field descriptions Field Description 7–1 Provides address bits 15 through 9 of the BDT base address. BDTBA This field is reserved. Reserved This read-only field is reserved and always has the value 0. 33.5.13 Frame Number register Low (USBx_FRMNUML) The Frame Number registers (low and high) contain the 11-bit frame number.
Page 553: Bdt Page Register 2 (Usbx_Bdtpage2)
Chapter 33 Universal Serial Bus (USB) FS Subsystem 33.5.15 BDT Page Register 2 (USBx_BDTPAGE2) Contains an 8-bit value used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table. Address: 4007_2000h base + B0h offset = 4007_20B0h Read BDTBA Write...
Page 554: Endpoint Control Register (Usbx_Endptn)
Memory map/Register definitions 33.5.17 Endpoint Control register (USBx_ENDPTn) Contains the endpoint control bits for each of the 16 endpoints available within the USB module for a decoded address. The format for these registers is shown in the following figure. Endpoint 0 (ENDPT0) is associated with control pipe 0, which is required for all USB functions.
Page 555: Usb Control Register (Usbx_Usbctrl)
Chapter 33 Universal Serial Bus (USB) FS Subsystem USBx_ENDPTn field descriptions (continued) Field Description causes the USB Module to return a STALL handshake. After an endpoint is stalled it requires intervention from the Host Controller. When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint. This EPHSHK bit is generally 1 unless the endpoint is Isochronous.
Page 556: Usb Otg Control Register (Usbx_Control)
Memory map/Register definitions USBx_OBSERVE field descriptions Field Description Provides observability of the D+ Pullup signal output from USB . DPPU D+ pullup disabled. D+ pullup enabled. Provides observability of the D+ Pulldown signal output from USB. DPPD D+ pulldown disabled. D+ pulldown enabled.
Page 557: Usb Transceiver Control Register 0 (Usbx_Usbtrc0)
Chapter 33 Universal Serial Bus (USB) FS Subsystem 33.5.21 USB Transceiver Control register 0 (USBx_USBTRC0) Includes signals for basic operation of the on-chip USB Full Speed transceiver and configuration of the USB data connection that are not otherwise included in the USB Full Speed controller registers.
Page 558: Frame Adjust Register (Usbx_Usbfrmadjust)
Memory map/Register definitions USBx_USBTRC0 field descriptions (continued) Field Description Combined USB Clock Recovery interrupt status USB_CLK_ This read-only field will be set to value high at 1'b1 when any of USB clock recovery interrupt conditions RECOVERY_INT are detected and those interrupts are unmasked. For customer use the only unmasked USB clock recovery interrupt condition results from an overflow of the frequency trim setting values indicating that the frequency trim calculated is out of the adjustment range of the IRC48M output clock.
Page 559: Irc48M Oscillator Enable Register (Usbx_Clk_Recover_Irc_En)
Chapter 33 Universal Serial Bus (USB) FS Subsystem Address: 4007_2000h base + 140h offset = 4007_2140h Read CLOCK_ RESET_ RESTART_ RECOVER_ RESUME_ IFRTRIM_ Reserved Reserved Reserved Reserved Write ROUGH_EN Reset USBx_CLK_RECOVER_CTRL field descriptions Field Description Crystal-less USB enable CLOCK_ This bit must be enabled if user wants to use the crystal-less USB mode for the Full Speed USB controller RECOVER_EN and transceiver.
Page 560: Clock Recovery Combined Interrupt Enable (Usbx_Clk_Recover_Int_En)
Memory map/Register definitions See additional information about the IRC48M operation in the Clock Distribution chapter. Address: 4007_2000h base + 144h offset = 4007_2144h Read Reserved IRC_EN Reserved Write Reset USBx_CLK_RECOVER_IRC_EN field descriptions Field Description 7–2 This field is reserved. Reserved IRC48M enable IRC_EN This bit is used to enable the on-chip IRC48Mhz module to generate clocks for crystal-less USB.
Page 561: Clock Recovery Separated Interrupt Status (Usbx_Clk_Recover_Int_Status)
Chapter 33 Universal Serial Bus (USB) FS Subsystem USBx_CLK_RECOVER_INT_EN field descriptions (continued) Field Description Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT. OVF_ERROR_ The interrupt will be masked The interrupt will be enabled (default) Reserved This field is reserved. Should always be written as 0.
Page 562 Device mode IRC48 operation 2. Enable the USB clock recovery tuning: USB_CLK_RECOVER_CTRL[CLOCK_RECOVER_EN] = 1b 3. Choose the clock source of USB by configuring the muxes in the SIM. MCG HIRC supplies the HIRC 48mhz clock by setting SIM_SOPT2[USBSRC] = 1b. 4.
Page 563: Usb Voltage Regulator (Vreg)
Chapter 34 USB Voltage Regulator (VREG) 34.1 Introduction The USB Voltage Regulator module is a LDO linear voltage regulator to provide 3.3V power from an input power supply varying from 2.7 V to 5.5 V. It consists of one 3.3 V power channel.
Page 564: Features
Introduction STANDBY Regulator Other Modules STANDBY Regulated Output reg33_out Voltage reg33_in Power RUN Regulator Supply ESR: 5m -> 100m Ohms Voltage Regulator Voltage Regulator External Capacitor Chip typical = 2.2uF Figure 34-2. USB Voltage Regulator Block Diagram This module uses 2 regulators in parallel. In run mode, the RUN regulator with the bandgap voltage reference is enabled and can provide up to 120 mA load current.
Page 565: Modes Of Operation
Chapter 34 USB Voltage Regulator (VREG) • Small output capacitor: 2.2 µF • Stable with aluminum, tantalum or ceramic capacitors. 34.1.3 Modes of Operation The regulator has these power modes: • RUN—The regulating loop of the RUN regulator and the STANDBY regulator are active, but the switch connecting the STANDBY regulator output to the external pin is open.
Page 566 USB Voltage Regulator Module Signal Descriptions KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 567: Serial Peripheral Interface (Spi)
Chapter 35 Serial Peripheral Interface (SPI) 35.1 Chip-specific SPI information This device contains two SPI modules that support 16-bit data length. SPI1 includes a 4- deep FIFO, SPI0 does not include FIFO. SPI0 is clocked on the bus clock. SPI1 is clocked from the system clock.
Page 568: Features
Introduction The SPI runs at a baud rate up to the SPI module clock divided by two in master mode and up to the SPI module clock divided by four in slave mode. Software can poll the status flags, or SPI operation can be interrupt driven. NOTE For the actual maximum SPI baud rate, refer to the Chip Configuration details and to the device’s Data Sheet.
Page 569: Modes Of Operation
Chapter 35 Serial Peripheral Interface (SPI) 35.2.2 Modes of operation The SPI functions in the following three modes. • Run mode This is the basic mode of operation. • Wait mode SPI operation in Wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPIx_C2 register.
Page 570 Introduction in (on the MISO pin) from the slave. The transfer effectively exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock output from the master and an input to the slave. The slave device must be selected by a low level on the slave select input (SS pin).
Page 571 Chapter 35 Serial Peripheral Interface (SPI) When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI pin.
Page 572: External Signal Description
External signal description PIN CONTROL MOSI Tx FIFO (64 bits deep) (MOMI) Tx BUFFER (WRITE DH:DL) ENABLE MISO SPI SYSTEM SPI SHIFT REGISTER (SISO) SHIFT SHIFT 8 OR 16 Rx BUFFER (READ DH:DL) SPIMODE SPC0 BIT MODE FIFOMODE Rx FIFO (64 bits deep) BIDIROE LSBFE SHIFT...
Page 573: Spsck - Spi Serial Clock
Chapter 35 Serial Peripheral Interface (SPI) 35.3.1 SPSCK — SPI Serial Clock When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master, this pin is the serial clock output. 35.3.2 MOSI —...
Page 574: Memory Map/Register Definition
Memory map/register definition 35.4 Memory map/register definition The SPI has 8-bit registers to select SPI options, to control baud rate, to report SPI status, to hold an SPI data match value, and for transmit/receive data. SPI memory map Absolute Width Section/ address Register name...
Page 575 Chapter 35 Serial Peripheral Interface (SPI) NOTE When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): Bits 3 through 0 are not implemented and always read 0. When the FIFO is supported and enabled (FIFOMODE is 1): This register has four flags that provide mechanisms to support an 8-byte FIFO mode: RNFULLF, TNEARF, TXFULLF, and RFIFOEF.
Page 576 Memory map/register definition SPIx_S field descriptions (continued) Field Description is 1), SPRF is automatically cleared when the DMA transfer for the receive DMA request is completed (RX DMA Done is asserted). When FIFOMODE is 1: This bit indicates the status of the read FIFO when FIFOMODE is enabled. The SPRF is set when the read FIFO has received 64 bits (4 words or 8 bytes) of data from the shifter and there have been no CPU reads of the SPI data (DH:DL) register.
Page 577 Chapter 35 Serial Peripheral Interface (SPI) SPIx_S field descriptions (continued) Field Description SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1) SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1) Master Mode Fault Flag MODF...
Page 578: Spi Baud Rate Register (Spix_Br)
Memory map/register definition SPIx_S field descriptions (continued) Field Description When FIFOMODE and DMA are both enabled, the inverted RXIFOEF is used to trigger a DMA transfer. So when the receive FIFO is not empty, the DMA request is active, and remains active until the FIFO is empty.
Page 579: Spi Control Register 2 (Spix_C2)
Chapter 35 Serial Peripheral Interface (SPI) SPIx_BR field descriptions (continued) Field Description This 4-bit field selects one of nine divisors for the SPI baud rate divider. The input to this divider comes from the SPI baud rate prescaler. Refer to the description of “SPI Baud Rate Generation” for details. 0000 Baud rate divisor is 2.
Page 580 Memory map/register definition SPIx_C2 field descriptions (continued) Field Description DMA request for transmit is disabled and interrupt from SPTEF is allowed DMA request for transmit is enabled and interrupt from SPTEF is disabled Master Mode-Fault Function Enable MODFEN When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used.
Page 581: Spi Control Register 1 (Spix_C1)
Chapter 35 Serial Peripheral Interface (SPI) 35.4.4 SPI Control Register 1 (SPIx_C1) This read/write register includes the SPI enable control, interrupt enables, and configuration options. Address: Base address + 3h offset Read SPIE SPTIE MSTR CPOL CPHA SSOE LSBFE Write Reset SPIx_C1 field descriptions Field...
Page 582: Spi Match Register Low (Spix_Ml)
Memory map/register definition SPIx_C1 field descriptions (continued) Field Description Clock Polarity CPOL Selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. This bit effectively places an inverter in series with the clock signal either from a master SPI device or to a slave SPI device.
Page 583: Spi Match Register High (Spix_Mh)
Chapter 35 Serial Peripheral Interface (SPI) In 16-bit mode, reading either byte (the MH or ML register) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. Writing to either byte (the MH or ML register) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent value into the SPI match registers.
Page 584: Spi Data Register High (Spix_Dh)
Memory map/register definition write is ignored. When the transmit DMA request is enabled (TXDMAE is 1) when S[SPTEF] is set, the SPI data registers can be written automatically by DMA without reading the S register first. Data may be read from the SPI data registers any time after S[SPRF] is set and before another transfer is finished.
Page 585: Spi Clear Interrupt Register (Spix_Ci)
Chapter 35 Serial Peripheral Interface (SPI) 35.4.9 SPI clear interrupt register (SPIx_CI) This register applies only for an instance of the SPI module that supports the FIFO feature. The register has four bits dedicated to clearing the interrupts. Writing 1 to these bits clears the corresponding interrupts if the INTCLR bit in the C3 register is 1.
Page 586: Spi Control Register 3 (Spix_C3)
Memory map/register definition SPIx_CI field descriptions (continued) Field Description Transmit FIFO overflow condition has not occurred Transmit FIFO overflow condition occurred Receive FIFO overflow flag RXFOF This flag indicates that a receive FIFO overflow condition has occurred. Receive FIFO overflow condition has not occurred Receive FIFO overflow condition occurred Transmit FIFO nearly empty flag clear interrupt TNEAREFCI...
Page 587 Chapter 35 Serial Peripheral Interface (SPI) Two interrupt enable bits, TNEARIEN and RNFULLIEN, provide CPU interrupts based on the "watermark" feature of the TNEARF and RNFULLF flags of the S register. Address: Base address + Bh offset Read TNEAREF_ RNFULLF_ INTCLR TNEARIEN RNFULLIEN FIFOMODE MARK...
Page 588: Functional Description
Functional description 35.5 Functional description This section provides the functional description of the module. 35.5.1 General The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1. While C1[SPE] is set, the four associated SPI port pins are dedicated to the SPI function •...
Page 589 Chapter 35 Serial Peripheral Interface (SPI) • SPSCK • The SPR3, SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI Baud Rate register control the baud rate generator and determine the speed of the transmission.
Page 590: Slave Mode
Functional description 35.5.3 Slave mode The SPI operates in slave mode when the MSTR bit in SPI Control Register 1 is clear. • SPSCK In slave mode, SPSCK is the SPI clock input from the master. • MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register •...
Page 591: Spi Fifo Mode
Chapter 35 Serial Peripheral Interface (SPI) If C1[CPHA] is set, even numbered edges on the SPSCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on C1[LSBFE].
Page 592: Spi Transmission By Dma
Functional description IPBus (ips_rdata[7:0]) Read Access SPI_REG_BLOCK SPI Data Register spidh:l_tx_reg TX- FIFO FIFO Ctrlr FIFO depth = 8 bytes SPI_CORE_SHFR Read shfr_tx_reg Control Figure 35-5. SPIH:L write side structural overview in FIFO mode 35.5.5 SPI Transmission by DMA SPI supports both Transmit and Receive by DMA. The basic flow of SPI transmission by DMA is as below.
Page 593 Chapter 35 Serial Peripheral Interface (SPI) 35.5.5.1 Transmit by DMA Transmit by DMA is supported only when TXDMAE is set. A transmit DMA request is asserted when both SPE and SPTEF are set. Then the on-chip DMA controller detects this request and transfers data from memory into the SPI data register. After that, TX DMA DONE is asserted to clear SPTEF automatically.
Page 594: Data Transmission Length
Functional description received (the number is decided by configuration register[s] of the DMA controller) is received or no receive DMA request is generated again because the SPI transmission is finished. When the FIFO feature is supported: In FIFO mode (FIFOMODE=1) and when a data length of 8 bits is selected (SPIMODE=0), the DMA transfer for one receive DMA request can read more than 1 byte (up to 8 bytes) from the SPI data register because the RX FIFO can hold 8 bytes.
Page 595: Spi Clock Formats
Chapter 35 Serial Peripheral Interface (SPI) In slave mode, user software should write to SPIMODE only once to prevent corrupting a transmission in progress. Note Data can be lost if the data length is not the same for both master and slave devices. 35.5.7 SPI clock formats To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI system has a Clock Polarity (CPOL) bit and a Clock Phase...
Page 596 Functional description BIT TIME # (REFERENCE) SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST BIT 7 BIT 6 BIT 2 BIT 1 BIT 0 LSB FIRST BIT 0 BIT 1 BIT 5 BIT 6 BIT 7...
Page 597 Chapter 35 Serial Peripheral Interface (SPI) Between these two successive transmissions, no pause is inserted; the SS pin remains low. The following figure shows the clock formats when SPIMODE = 0 and C1[CPHA] = 0. At the top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge.
Page 598: Spi Baud Rate Generation
Functional description When C1[CPHA] = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively.
Page 599 Chapter 35 Serial Peripheral Interface (SPI) 35.5.9.1 SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives the SS pin high during idle to deselect external devices. When the SS output is selected, the SS output pin is connected to the SS input pin of the external device.
Page 600: Error Conditions
Functional description SS is the input or output for the master mode, and it is always the input for the slave mode. The bidirectional mode does not affect SPSCK and SS functions. Note In bidirectional master mode, with the mode fault feature enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI.
Page 601: Low-Power Mode Options
Chapter 35 Serial Peripheral Interface (SPI) The mode fault flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed by a write to SPI Control Register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again. 35.5.11 Low-power mode options This section describes the low-power mode options.
Page 602: Reset
Functional description Note Care must be taken when expecting data from a master while the slave is in a Wait mode or a Stop mode where the peripheral bus clock is stopped but internal logic states are retained. Even though the shift register continues to operate, the rest of the SPI is shut down (that is, an SPRF interrupt is not generated until an exit from Stop or Wait mode).
Page 603: Interrupts
Chapter 35 Serial Peripheral Interface (SPI) 35.5.13 Interrupts The SPI originates interrupt requests only when the SPI is enabled (the SPE bit in the SPIx_C1 register is set). The following is a description of how the SPI makes a request and how the MCU should acknowledge that request.
Page 604 Functional description After SPRF is set, it does not clear until it is serviced. SPRF has an automatic clearing process that is described in the SPI Status Register details. If the SPRF is not serviced before the end of the next transfer (that is, SPRF remains active throughout another transfer), the subsequent transfers are ignored and no new data is copied into the Data register.
Page 605: Initialization/Application Information
Chapter 35 Serial Peripheral Interface (SPI) RNFULLF is set when more than three 16-bit words or six 8-bit bytes of data remain in the receive FIFO provided C3[4] = 0 or when more than two 16-bit words or four 8-bit bytes of data remain in the receive FIFO provided C3[4] = 1.
Page 606: Pseudo-Code Example
Initialization/application information 1. Update the Control Register 1 (SPIx_C1) to enable the SPI and to control interrupt enables. This register also sets the SPI as master or slave, determines clock phase and polarity, and configures the main SPI options. 2. Update the Control Register 2 (SPIx_C2) to enable additional SPI functions such as the SPI match interrupt feature, the master mode-fault function, and bidirectional mode output as well as to control 8- or 16-bit mode selection and other optional features.
Page 607 Chapter 35 Serial Peripheral Interface (SPI) SPIx_C2 = 0xC0(%11000000) Bit 3 BIDIROE SPI data I/O pin acts as input Bit 2 RXDMAE DMA request disabled Bit 1 SPISWAI SPI clocks operate in wait mode Bit 0 SPC0 uses separate pins for data input and output SPIx_BR = 0x00(%00000000) Bit 7 Reserved...
Page 608 Initialization/application information RESET INITIALIZE SPI SPIxC1 = 0x54 0xC0 SPIxC2 = SPIxBR = 0x00 SPIxMH = 0xXX SPTEF = 1 WRITE TO SPIxDH:SPIxDL SPRF = 1 READ SPIxDH:SPIxDL SPMF = 1 READ SPMF WHILE SET TO CLEAR FLAG, THEN WRITE A 1 TO IT CONTINUE Figure 35-10.
Page 609 Chapter 35 Serial Peripheral Interface (SPI) RESET INITIALIZE SPI SPIxC1 = 0x54 SPIxC2 = 0xC0 SPIxBR = 0x00 SPIxMH = 0xXX Set FIFOMODE WRITE TO SPIxDH:SPIxDL TXFULLF = 1 RNFULLF = 1/ SPRF = 1 READ SPIxDH:SPIxDL RFIFOEF = 1 CONTINUE Figure 35-11.
Page 610 Initialization/application information KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 611: Inter-Integrated Circuit (I2C)
Chapter 36 Inter-Integrated Circuit (I2C) 36.1 Chip-specific I2C information 36.1.1 I2C instantiation information This device has two IIC modules. I2Cx are clocked by the system clock so they can support standard IIC communication rates of 100 kbit/s in VLPR mode. When the package pins associated with IIC have their mux select configured for IIC operation, the pins (SCL and SDA) are driven either by true open drain or in a pseudo open drain configuration.
Page 612: Features
Introduction number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. The I2C module also complies with the System Management Bus (SMBus) Specification, version 2. 36.2.1 Features The I2C module has the following features: •...
Page 613: Block Diagram
Chapter 36 Inter-Integrated Circuit (I2C) 36.2.3 Block diagram The following figure is a functional block diagram of the I2C module. Module Enable Address Write/Read Interrupt DATA_MUX ADDR_DECODE DATA_REG CTRL_REG ADDR_REG FREQ_REG STATUS_REG Input Sync In/Out START Data STOP Shift Arbitration Register Control Clock...
Page 614: Memory Map/Register Definition
Memory map/register definition 36.4 Memory map/register definition This section describes in detail all I2C registers accessible to the end user. I2C memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4006_6000 I2C Address Register 1 (I2C0_A1) 36.4.1/615 4006_6001 I2C Frequency Divider register (I2C0_F)
Page 615: I2C Address Register 1 (I2Cx_A1)
Chapter 36 Inter-Integrated Circuit (I2C) 36.4.1 I2C Address Register 1 (I2Cx_A1) This register contains the slave address to be used by the I2C module. Address: Base address + 0h offset Read AD[7:1] Write Reset I2Cx_A1 field descriptions Field Description 7–1 Address AD[7:1] Contains the primary slave address used by the I2C module when it is addressed as a slave.
Page 616: I2C Control Register 1 (I2Cx_C1)
Memory map/register definition I2Cx_F field descriptions (continued) Field Description The SDA hold time is the delay from the falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time = I2C module clock period (s) × mul × SDA hold value The SCL start hold time is the delay from the falling edge of SDA (I2C data) while SCL is high (start condition) to the falling edge of SCL (I2C clock).
Page 617 Chapter 36 Inter-Integrated Circuit (I2C) I2Cx_C1 field descriptions (continued) Field Description Disabled Enabled Master Mode Select When MST is changed from 0 to 1, a START signal is generated on the bus and master mode is selected. When this bit changes from 1 to 0, a STOP signal is generated and the mode of operation changes from master to slave.
Page 618: I2C Status Register (I2Cx_S)
Memory map/register definition I2Cx_C1 field descriptions (continued) Field Description If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case.
Page 619 Chapter 36 Inter-Integrated Circuit (I2C) I2Cx_S field descriptions (continued) Field Description Indicates the status of the bus regardless of slave or master mode. This bit is set when a START signal is detected and cleared when a STOP signal is detected. Bus is idle Bus is busy Arbitration Lost...
Page 620: I2C Data I/O Register (I2Cx_D)
Memory map/register definition I2Cx_S field descriptions (continued) Field Description Acknowledge signal was received after the completion of one byte of data transmission on the bus No acknowledge signal detected 36.4.5 I2C Data I/O register (I2Cx_D) Address: Base address + 4h offset Read DATA Write...
Page 621: I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
Chapter 36 Inter-Integrated Circuit (I2C) I2Cx_C2 field descriptions Field Description General Call Address Enable GCAEN Enables general call address. Disabled Enabled Address Extension ADEXT Controls the number of bits used for the slave address. 7-bit address scheme 10-bit address scheme High Drive Select HDRS Controls the drive capability of the I2C pads.
Page 622 Memory map/register definition I2Cx_FLT field descriptions Field Description Stop Hold Enable SHEN Set this bit to hold off entry to stop mode when any data transmission or reception is occurring. The following scenario explains the holdoff functionality: 1. The I2C module is configured for a basic transfer, and the SHEN bit is set to 1. 2.
Page 623: I2C Range Address Register (I2Cx_Ra)
Chapter 36 Inter-Integrated Circuit (I2C) I2Cx_FLT field descriptions (continued) Field Description Controls the width of the glitch, in terms of I2C module clock cycles, that the filter must absorb. For any glitch whose size is less than or equal to this width setting, the filter does not allow the glitch to pass. No filter/bypass 1-Fh Filter glitches up to width of n I2C module clock cycles, where n=1-15d...
Page 624 Memory map/register definition Address: Base address + 8h offset Read SLTF SHTF1 SHTF2 FACK ALERTEN SIICAEN TCKSEL SHTF2IE Write Reset I2Cx_SMB field descriptions Field Description Fast NACK/ACK Enable FACK For SMBus packet error checking, the CPU must be able to issue an ACK or NACK according to the result of receiving data byte.
Page 625: I2C Address Register 2 (I2Cx_A2)
Chapter 36 Inter-Integrated Circuit (I2C) I2Cx_SMB field descriptions (continued) Field Description SCL High Timeout Flag 2 SHTF2 This bit sets when SCL is held high and SDA is held low more than clock × LoValue / 512. Software clears this bit by writing 1 to it. No SCL high and SDA low timeout occurs SCL high and SDA low timeout occurs SHTF2 Interrupt Enable...
Page 626: I2C Scl Low Timeout Register Low (I2Cx_Sltl)
Memory map/register definition 36.4.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL) Address: Base address + Bh offset Read SSLT[7:0] Write Reset I2Cx_SLTL field descriptions Field Description SSLT[7:0] SSLT[7:0] Least significant byte of SCL low timeout value that determines the timeout period of SCL low. 36.4.13 I2C Status register 2 (I2Cx_S2) Address: Base address + Ch offset Read...
Page 627: Functional Description
Chapter 36 Inter-Integrated Circuit (I2C) I2Cx_S2 field descriptions (continued) Field Description Empty flag EMPTY Indicates if the Tx or Rx buffer is empty. Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer.
Page 628 Functional description AD6 AD5 D7 D6 D4 D3 D2 D1 AD3 AD2 AD1 Start Calling Address Read/ Data Byte Stop Signal Signal Write AD3 AD2 AD1 AD3 AD2 AD1 Repeated Calling Address Read/ New Calling Address Start Stop Read/ Start Signal Signal Write...
Page 629 Chapter 36 Inter-Integrated Circuit (I2C) No two slaves in the system can have the same address. If the I2C module is the master, it must not transmit an address that is equal to its own slave address. The I2C module cannot be master and slave at the same time.
Page 630 Functional description 36.5.1.5 Repeated START signal The master may generate a START signal followed by a calling command without generating a STOP signal first. This action is called a repeated START. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.The master needs to send a NACK signal before sending repeated-START in the buffering mode.
Page 631 Chapter 36 Inter-Integrated Circuit (I2C) Start Counting High Period Delay SCL2 SCL1 Internal Counter Reset Figure 36-3. I2C clock synchronization 36.5.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfers. A slave device may hold SCL low after completing a single byte transfer (9 bits). In this case, it halts the bus clock and forces the master clock into wait states until the slave releases SCL.
Page 632: 10-Bit Address
Functional description Table 36-2. I2C divider and hold values SDA hold SCL hold SCL hold SDA hold SCL hold SCL hold divider value (start) (stop) divider (clocks) (start) (stop) (hex) (hex) value value (clocks) value value 1024 1152 1280 1536 1920 1280 1536...
Page 633 Chapter 36 Inter-Integrated Circuit (I2C) 36.5.2 10-bit address For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 36.5.2.1 Master-transmitter addresses a slave-receiver The transfer direction is not changed.
Page 634: Address Matching
Functional description After a repeated START condition (Sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit devices), or the 11110XX slave address (for 7-bit devices) does not match.
Page 635: System Management Bus Specification
Chapter 36 Inter-Integrated Circuit (I2C) 36.5.4 System management bus specification SMBus provides a control bus for system and power management related tasks. A system can use SMBus to pass messages to and from devices instead of tripping individual control lines. Removing the individual control lines reduces pin count.
Page 636 Functional description 36.5.4.1.2 SCL high timeout When the I2C module has determined that the SMBCLK and SMBDAT signals have been high for at least T , it assumes that the bus is idle. HIGH:MAX A HIGH timeout occurs after a START condition appears on the bus but before a STOP condition appears on the bus.
Page 637: Resets
Chapter 36 Inter-Integrated Circuit (I2C) NOTE CSMBCLK TIMEOUT SEXT and CSMBCLK TIMEOUT MEXT are optional functions that are implemented in the second step. 36.5.4.2 FAST ACK and NACK To improve reliability and communication robustness, implementation of packet error checking (PEC) by SMBus devices is optional for SMBus devices but required for devices participating in and only during the address resolution protocol (ARP) process.
Page 638: Interrupts
Functional description 36.5.6 Interrupts The I2C module generates an interrupt when any of the events in the table found here occur, provided that the IICIE bit is set. The interrupt is driven by the IICIF bit (of the I2C Status Register) and masked with the IICIE bit (of the I2C Control Register 1).
Page 639 Chapter 36 Inter-Integrated Circuit (I2C) 36.5.6.3 Stop Detect Interrupt When the stop status is detected on the I C bus, the STOPF bit is set to 1. The CPU is interrupted, provided the IICIE and SSIE bits are both set to 1. 36.5.6.4 Exit from low-power/stop modes The slave receive input detect circuit and address matching feature are still active on low power modes (wait and stop).
Page 640: Programmable Input Glitch Filter
Functional description 36.5.6.6 Timeout interrupt in SMBus When the IICIE bit is set, the I2C module asserts a timeout interrupt (outputs SLTF and SHTF2) upon detection of any of the mentioned timeout conditions, with one exception. The SCL high and SDA high TIMEOUT mechanism must not be used to influence the timeout interrupt output, because this timeout indicates an idle condition on the bus.
Page 641: Dma Support
Chapter 36 Inter-Integrated Circuit (I2C) After the address matching IAAS bit is set, an interrupt is sent at the end of address matching to wake the core. The IAAS bit must be cleared after the clock recovery. NOTE After the system recovers and is in Run mode, restart the I2C module if it is needed to transfer packets.
Page 642: Double Buffering Mode
Functional description 36.5.10 Double buffering mode In the double buffering mode, the data transfer is processed byte by byte. However, the data can be transferred without waiting for the interrupt or the polling to finish. This means the write/read I2C_D operation will not block the data transfer, as the hardware has already finished the internal write or read.
Page 643: Initialization/Application Information
Chapter 36 Inter-Integrated Circuit (I2C) 36.6 Initialization/application information Module Initialization (Slave) 1. Write: Control Register 2 • to enable or disable general call • to select 10-bit or 7-bit addressing mode 2. Write: Address Register 1 to set the slave address 3.
Page 644 Initialization/application information Clear STOPF Is STOPF Entry of ISR Clear IICIF set? Zero Start Count Clear STARTF Is STARTF Clear IICIF set? Log Start Count++ Is this a Repeated-START Clear IICIF (Start Count > 1)? Master mode? Arbitration Tx/Rx? lost? Last byte Clear ARBL transmitted?
Page 645 Chapter 36 Inter-Integrated Circuit (I2C) Entry of ISR SLTF=1 or SHTF2=1? See typical I2C FACK=1? interrupt routine flow chart Clear IICIF Master mode? Arbitration Tx/Rx? lost? Last byte Clear ARBL transmitted? Last byte to be RXAK=0? IAAS=1? IAAS=1? read? Read data from Address transfer Data reg (see Note 1)
Page 646 Initialization/application information KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 647: Low Power Universal Asynchronous Receiver/Transmitter (Lpuart)
Chapter 37 Low Power Universal asynchronous receiver/ transmitter (LPUART) 37.1 Chip-specific LPUART information 37.1.1 LPUART0 and LPUART1 overview These modules supports basic UART with DMA interface function, x4 to x32 oversampling of baud-rate. This module supports LIN slave operation. The module can remain functional in VLPS mode provided the clock it is using remains enabled.
Page 648: Modes Of Operation
Introduction • Receive data register full • Receive overrun, parity error, framing error, and noise error • Idle receiver detect • Active edge on receive pin • Break detect supporting LIN • Receive data match • Hardware parity generation and checking •...
Page 649: Signal Descriptions
Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) 37.2.2.3 Debug mode The LPUART remains functional in debug mode. 37.2.3 Signal Descriptions Signal Description LPUART_TX Transmit data. This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or transmit direction is configured for receive data.
Page 650 Introduction Internal Bus (Write-Only) LOOPS ASYNCH LPUART_D – Tx Buffer MODULE RSRC CLOCK Loop To Receive 11-BIT Transmit Shift Register Control BAUD Data In Divider To TxD Pin  Divider SHIFT DIRECTION TXINV Parity Generation LPUART Controls TxD TO TxD Transmit Control Pin Logic TxD Direction...
Page 651: Register Definition
Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) INTERNAL BUS SBR12:0 DATA BUFFER ASYNCH BAUDRATE MODULE VARIABLE 12-BIT RECEIVE CLOCK GENERATOR SHIFT REGISTER LBKDE RECEIVE MSBF CONTROL RXINV SHIFT DIRECTION LOOPS RECEIVER RSRC SOURCE CONTROL PARITY WAKEUP LOGIC LOGIC From Transmitter DMA Requests IRQ / DMA ACTIVE EDGE...
Page 652: Lpuart Baud Rate Register (Lpuartx_Baud)
Register definition 37.3.1 LPUART Baud Rate Register (LPUARTx_BAUD) Address: Base address + 0h offset MATCFG Reset SBNS Reset LPUARTx_BAUD field descriptions Field Description Match Address Mode Enable 1 MAEN1 Normal operation. Enables automatic address matching or data matching mode for MATCH[MA1]. Match Address Mode Enable 2 MAEN2 Normal operation.
Page 653 Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) LPUARTx_BAUD field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Receiver Full DMA Enable RDMAE RDMAE configures the receiver data register full flag, LPUART_STAT[RDRF], to generate a DMA request. DMA request disabled.
Page 654: Lpuart Status Register (Lpuartx_Stat)
Register definition LPUARTx_BAUD field descriptions (continued) Field Description One stop bit. Two stop bits. Baud Rate Modulo Divisor. The 13 bits in SBR[12:0] set the modulo divide rate for the baud rate generator. When SBR is 1 - 8191, the baud rate equals "baud clock / ((OSR+1) × SBR)". The 13-bit baud rate setting [SBR12:SBR0] must only be updated when the transmitter and receiver are both disabled (LPUART_CTRL[RE] and LPUART_CTRL[TE] are both 0).
Page 655 Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) LPUARTx_STAT field descriptions (continued) Field Description No LIN break character has been detected. LIN break character has been detected. LPUART_RX Pin Active Edge Interrupt Flag RXEDGIF RXEDGIF is set when an active edge, falling if RXINV = 0, rising if RXINV=1, on the LPUART_RX pin occurs.
Page 656 Register definition LPUARTx_STAT field descriptions (continued) Field Description Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
Page 657 Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) LPUARTx_STAT field descriptions (continued) Field Description No idle line detected. Idle line was detected. Receiver Overrun Flag OR is set when software fails to prevent the receive data register from overflowing with data. The OR bit is set immediately after the stop bit has been completely received for the dataword that overflows the buffer and all the other error flags (FE, NF, and PF) are prevented from setting.
Page 658: Lpuart Control Register (Lpuartx_Ctrl)
Register definition LPUARTx_STAT field descriptions (continued) Field Description Reserved This field is reserved. This read-only field is reserved and always has the value 0. 37.3.3 LPUART Control Register (LPUARTx_CTRL) This read/write register controls various optional features of the LPUART system. This register should only be altered when the transmitter and receiver are both disabled.
Page 659 Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) LPUARTx_CTRL field descriptions (continued) Field Description LPUART_TX Pin Direction in Single-Wire Mode TXDIR When the LPUART is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines the direction of data at the LPUART_TX pin. When clearing TXDIR, the transmitter will finish receiving the current character (if any) before the receiver starts receiving data from the LPUART_TX pin.
Page 660 Register definition LPUARTx_CTRL field descriptions (continued) Field Description Receiver Interrupt Enable Enables STAT[RDRF] to generate interrupt requests. Hardware interrupts from RDRF disabled; use polling. Hardware interrupt requested when RDRF flag is 1. Idle Line Interrupt Enable ILIE ILIE enables the idle line flag, STAT[IDLE], to generate interrupt requests. Hardware interrupts from IDLE disabled;...
Page 661 Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) LPUARTx_CTRL field descriptions (continued) Field Description MA1F interrupt disabled MA1F interrupt enabled Match 2 Interrupt Enable MA2IE MA2F interrupt disabled MA2F interrupt enabled 13–11 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 10–8 Idle Configuration IDLECFG...
Page 662 Register definition LPUARTx_CTRL field descriptions (continued) Field Description Configures RWU for idle-line wakeup. Configures RWU with address-mark wakeup. Idle Line Type Select Determines when the receiver starts counting logic 1s as idle character bits. The count begins either after a valid start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit can cause false recognition of an idle character.
Page 663: Lpuart Data Register (Lpuartx_Data)
Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) 37.3.4 LPUART Data Register (LPUARTx_DATA) This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for some of the LPUART status flags.
Page 664 Register definition LPUARTx_DATA field descriptions (continued) Field Description The dataword was received without a parity error. The dataword was received with a parity error. Frame Error / Transmit Special Character FRETSC For reads, indicates the current received dataword contained in DATA[R9:R0] was received with a frame error.
Page 665: Lpuart Match Address Register (Lpuartx_Match)
Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) 37.3.5 LPUART Match Address Register (LPUARTx_MATCH) Address: Base address + 10h offset Reset LPUARTx_MATCH field descriptions Field Description 31–26 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 25–16 Match Address 2 The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and...
Page 666: Transmitter Functional Description
Functional description while the transmitter is driven by the baud rate clock divided by the over sampling ratio. Depending on the over sampling ratio, the receiver has an acquisition rate of 4 to 32 samples per bit time. Modulo Divide By (1 through 8191) Divide By Tx Baud Rate...
Page 667 Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) If no new character is waiting in the transmit data buffer after a stop bit is shifted out the LPUART_TX pin, the transmitter sets the transmit complete flag and enters an idle mode, with LPUART_TX high, waiting for more characters to transmit.
Page 668: Receiver Functional Description
Functional description Table 37-1. Break character length BRK13 SBNS Break character length 10 bit times 11 bit times 11 bit times 12 bit times 12 bit times 13 bit times 13 bit times 13 bit times 14 bit times 14 bit times 15 bit times 15 bit times 37.4.3 Receiver functional description...
Page 669 Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) When a program detects that the receive data register is full (LPUART_STAT[RDRF] = 1), it gets the data from the receive data register by reading LPUART_DATA. Refer to Interrupts and status flags for details about flag clearing.
Page 670 Functional description 37.4.3.2 Receiver wakeup operation Receiver wakeup and receiver address matching is a hardware mechanism that allows an LPUART receiver to ignore the characters in a message intended for a different receiver. During receiver wakeup, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up control bit (LPUART_CTRL[RWU]).
Page 671 Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) 37.4.3.2.1 Idle-line wakeup When wake is cleared, the receiver is configured for idle-line wakeup. In this mode, LPUART_CTRL[RWU] is cleared automatically when the receiver detects a full character time of the idle-line level. The LPUART_CTRL[M] and LPUART_BAUD[M10] control bit selects 8-bit to 10-bit data mode and the LPUART_BAUD[SBNS] bit selects 1-bit or 2-bit stop bit number that determines how many bit times of idle are needed to constitute a full character time, 10 to 13 bit times...
Page 672 Functional description 37.4.3.2.3 Data match wakeup When LPUART_CTRL[RWU] is set and LPUART_BAUD[MATCFG] equals 11, the receiver is configured for data match wakeup. In this mode, LPUART_CTRL[RWU] is cleared automatically when the receiver detects a character that matches MATCH[MA1] field when BAUD[MAEN1] is set, or that matches MATCH[MA2] when BAUD[MAEN2] is set.
Page 673: Additional Lpuart Functions
Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) considered to be data associated with the address and are transferred to the receive data buffer until the next idle line condition is detected. If no address match occurs then no transfer is made to the receive data buffer, and all following frames until the next idle condition are also discarded.
Page 674 Functional description 37.4.4.1 8-bit, 9-bit and 10-bit data modes The LPUART transmitter and receiver can be configured to operate in 9-bit data mode by setting the LPUART_CTRL[M] or 10-bit data mode by setting LPUART_CTRL[M10]. In 9-bit mode, there is a ninth data bit in 10-bit mode there is a tenth data bit. For the transmit data buffer, these bits are stored in LPUART_CTRL[T8] and LPUART_CTRL[T9].
Page 675: Interrupts And Status Flags
Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART) Idle-line wakeup and idle match operation are also affected by the CTRL[IDLECFG] field. When address match or match on/off operation is enabled, setting the STAT[RWUID] bit will cause any discarded characters to be treated as if they were idle characters.
Page 676 Functional description flag is often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable (LPUART_CTRL[TCIE]) bit is set, a hardware interrupt is requested when LPUART_STAT[TC] is set. Instead of hardware interrupts, software polling may be used to monitor the LPUART_STAT[TDRE] and LPUART_STAT[TC] status flags if the corresponding LPUART_CTRL[TIE] or LPUART_CTRL[TCIE] local interrupt masks are cleared.
Page 677: Universal Asynchronous Receiver/Transmitter(Uart)
Chapter 38 Universal Asynchronous Receiver/ Transmitter(UART) 38.1 Chip-specific UART information 38.1.1 UART2 Overview This device contains a basic universal asynchronous receiver/transmitter (UART) modules with DMA function support. Generally, these modules are used in RS-232, RS-485, and other communications. This module supports LIN Slave operation. 38.2 Introduction The UART allows asynchronous serial communication with peripheral devices and CPUs.
Page 678 Introduction • Programmable transmitter output polarity • Programmable receive input polarity • Up to 14-bit break character transmission. • 11-bit break character detection option • Two receiver wakeup methods: • Idle line wakeup • Address mark wakeup • Address match feature in the receiver to reduce address mark wakeup ISR overhead •...
Page 679: Modes Of Operation
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) • Idle receiver input • Receiver data buffer overrun • Noise error • Framing error • Parity error • Active edge on receive pin • Receiver framing error detection • Hardware parity generation and checking •...
Page 680: Uart Signal Descriptions
UART signal descriptions 38.3 UART signal descriptions The UART signals are shown in the following table. Table 38-1. UART signal descriptions Signal Description Receive data Transmit data 38.3.1 Detailed signal descriptions The detailed signal descriptions of the UART are shown in the following table. Table 38-2.
Page 681 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) UART memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4006_C001 UART Baud Rate Registers: Low (UART2_BDL) 38.4.2/683 4006_C002 UART Control Register 1 (UART2_C1) 38.4.3/683 4006_C003 UART Control Register 2 (UART2_C2) 38.4.4/685 4006_C004 UART Status Register 1 (UART2_S1) 38.4.5/687...
Page 682: Uart Baud Rate Registers: High (Uartx_Bdh)
Memory map and registers UART memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) UART 7816 Wait and Guard Parameter Register 38.4.27/ 4006_C03E (UART2_WGP7816_T1) UART 7816 Wait Parameter Register C 38.4.28/ 4006_C03F (UART2_WP7816C_T1) 38.4.1 UART Baud Rate Registers: High (UARTx_BDH) This register, along with the BDL register, controls the prescale divisor for UART baud rate generation.
Page 683: Uart Baud Rate Registers: Low (Uartx_Bdl)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) 38.4.2 UART Baud Rate Registers: Low (UARTx_BDL) This register, along with the BDH register, controls the prescale divisor for UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0], first write to BDH to buffer the high half of the new value and then write to BDL.
Page 684 Memory map and registers UARTx_C1 field descriptions (continued) Field Description Normal operation. Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. Reserved. Reserved This field is reserved. Receiver Source Select RSRC This field has no meaning or effect unless the LOOPS field is set.
Page 685: Uart Control Register 2 (Uartx_C2)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) UARTx_C1 field descriptions (continued) Field Description Determines whether the UART generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.
Page 686 Memory map and registers UARTx_C2 field descriptions (continued) Field Description IDLE interrupt requests disabled. IDLE interrupt requests enabled. Transmitter Enable Enables the UART transmitter. TE can be used to queue an idle preamble by clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been transmitted.
Page 687: Uart Status Register 1 (Uartx_S1)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) 38.4.5 UART Status Register 1 (UARTx_S1) The S1 register provides inputs to the MCU for generation of UART interrupts or DMA requests. This register can also be polled by the MCU to check the status of its fields. To clear a flag, the status register should be read followed by a read or write to D register, depending on the interrupt flag type.
Page 688 Memory map and registers UARTx_S1 field descriptions (continued) Field Description Receive data buffer is empty. Receive data buffer is full. Idle Line Flag IDLE After the IDLE flag is cleared, a frame must be received (although not necessarily stored in the data buffer, for example if C2[RWU] is set).
Page 689: Uart Status Register 2 (Uartx_S2)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) UARTx_S1 field descriptions (continued) Field Description No parity error detected. Parity error. 38.4.6 UART Status Register 2 (UARTx_S2) The S2 register provides inputs to the MCU for generation of UART interrupts or DMA requests. Also, this register can be polled by the MCU to check the status of these bits. This register can be read or written at any time, with the exception of the MSBF and RXINV bits, which should be changed by the user only between transmit and receive packets.
Page 690 Memory map and registers UARTx_S2 field descriptions (continued) Field Description Setting this field reverses the polarity of the received data input. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
Page 691: Uart Control Register 3 (Uartx_C3)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) 38.4.7 UART Control Register 3 (UARTx_C3) Writing R8 does not have any effect. TXDIR and TXINV can be changed only between transmit and receive packets. Address: 4006_C000h base + 6h offset = 4006_C006h Read TXDIR TXINV ORIE NEIE...
Page 692: Uart Data Register (Uartx_D)
Memory map and registers UARTx_C3 field descriptions (continued) Field Description Transmit data is not inverted. Transmit data is inverted. Overrun Error Interrupt Enable ORIE Enables the overrun error flag, S1[OR], to generate interrupt requests. OR interrupts are disabled. OR interrupt requests are enabled. Noise Error Interrupt Enable NEIE Enables the noise flag, S1[NF], to generate interrupt requests.
Page 693: Uart Match Address Registers 1 (Uartx_Ma1)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) stores the data in a temporary register. If D register is written first, and then the new data on data bus is stored in D, the temporary value written by the last write to C3[T8] gets stored in the C3[T8] register.
Page 694: Uart Match Address Registers 2 (Uartx_Ma2)
Memory map and registers 38.4.10 UART Match Address Registers 2 (UARTx_MA2) These registers can be read and written at anytime. The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4[MAEN] field is set.
Page 695: Uart Control Register 5 (Uartx_C5)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) UARTx_C4 field descriptions (continued) Field Description 10-bit Mode select Causes a tenth, non-memory mapped bit to be part of the serial transmission. This tenth bit is generated and interpreted as a parity bit. If M10 is set, then both C1[M] and C1[PE] must also be set. This field must be cleared when C7816[ISO7816E] is set/enabled.
Page 696: Uart 7816 Control Register (Uartx_C7816)
Memory map and registers UARTx_C5 field descriptions (continued) Field Description If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
Page 697: Uart 7816 Interrupt Enable Register (Uartx_Ie7816)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) UARTx_C7816 field descriptions (continued) Field Description No NACK is automatically generated. A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected. Detect Initial Character INIT When this field is set, all received characters are searched for a valid initial character. If an invalid initial character is identified, and ANACK is set, a NACK is sent.
Page 698 Memory map and registers UARTx_IE7816 field descriptions Field Description Wait Timer Interrupt Enable The assertion of IS7816[WT] does not result in the generation of an interrupt. The assertion of IS7816[WT] results in the generation of an interrupt. Character Wait Timer Interrupt Enable CWTE The assertion of IS7816[CWT] does not result in the generation of an interrupt.
Page 699: Uart 7816 Interrupt Status Register (Uartx_Is7816)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) 38.4.15 UART 7816 Interrupt Status Register (UARTx_IS7816) The IS7816 register provides a mechanism to read and clear the interrupt flags. All flags/ interrupts are cleared by writing a 1 to the field location. Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only the flag condition that occurred since the last time the bit was cleared, not that the condition currently exists.
Page 700 Memory map and registers UARTx_IS7816 field descriptions (continued) Field Description A valid initial character has not been received. A valid initial character has been received. ATR Duration Time Interrupt Indicates that the ATR duration time, the time between the leading edge of the TS character being received and the leading edge of the next response character, has exceeded the programmed value.
Page 701: Uart 7816 Wait Parameter Register (Uartx_Wp7816)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) 38.4.16 UART 7816 Wait Parameter Register (UARTx_WP7816) The WP7816 register contains the WTX variable used in the generation of the block wait timer. This register may be read at any time. This register must be written to only when C7816[ISO_7816E] is not set.
Page 702: Uart 7816 Wait Fd Register (Uartx_Wf7816)
Memory map and registers 38.4.18 UART 7816 Wait FD Register (UARTx_WF7816) The WF7816 contains parameters that are used in the generation of various counters including GT, CGT, BGT, WT, and BWT. This register may be read at any time. This register must be written to only when C7816[ISO_7816E] is not set.
Page 703: Uart 7816 Transmit Length Register (Uartx_Tl7816)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) UARTx_ET7816 field descriptions (continued) Field Description RXTHRESHOLD Receive NACK Threshold The value written to this field indicates the maximum number of consecutive NACKs generated as a result of a parity error or receiver buffer overruns before the host processor is notified. After the counter exceeds that value in the field, the IS7816[RXT] is asserted.
Page 704: Uart 7816 Atr Duration Timer Register B (Uartx_Ap7816B_T0)
Memory map and registers NOTE The ADT Counter starts counting on detection of the complete TS Character. It must be noted that by this time, exactly 10 ETUs have elapsed since the start bit of the TS character. The user must take this into account while programming this register.
Page 705: Uart 7816 Wait Parameter Register A (Uartx_Wp7816A_T0)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) UARTx_AP7816B_T0 field descriptions (continued) Field Description Used to calculate the value used for the ADT counter. This register field provides the least significant byte of the 16 bit ATR Duration Time Integer field ADTI formed by {AP7816A_T0[ADTI_H], AP7816B_T0[ADTI_L]}.
Page 706: Uart 7816 Wait Parameter Register B (Uartx_Wp7816B_T0)
Memory map and registers UARTx_WP7816A_T1 field descriptions Field Description BWI_H Block Wait Time Integer High (C7816[TTYPE] = 1) Used to calculate the value used for the BWT counter. This register field provides the most significant byte of the 16 bit Block Wait Time Integer field BWI formed by {WP7816A_T1[BWI_H], WP7816B_T1[BWI_L]}. The value of BWI = 0 is invalid and should not be programmed.
Page 707: Uart 7816 Wait And Guard Parameter Register (Uartx_Wgp7816_T1)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) UARTx_WP7816B_T1 field descriptions Field Description BWI_L Block Wait Time Integer Low (C7816[TTYPE] = 1) Used to calculate the value used for the BWT counter. This register field provides the least significant byte of the 16 bit Block Wait Time Integer field BWI formed by {WP7816A_T1[BWI_H], WP7816B_T1[BWI_L]}. The value of BWI = 0 is invalid and should not be programmed.
Page 708: Functional Description
Functional description UARTx_WP7816C_T1 field descriptions Field Description 7–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CWI2 Character Wait Time Integer 2 (C7816[TTYPE] = 1) Used to calculate the value used for the CWT counter. It represents a value between 0 and 31. This value is used only when C7816[TTYPE] = 1.
Page 709 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) 38.5.1 Transmitter Figure 38-1. Transmitter Block Diagram 38.5.1.1 Transmitter character length The UART transmitter can accommodate either 8, 9, or 10-bit data characters. The state of the C1[M] and C1[PE] bits and the C4[M10] bit determine the length of data characters.
Page 710 Functional description 38.5.1.2 Transmission bit order When S2[MSBF] is set, the UART automatically transmits the MSB of the data word as the first bit after the start bit. Similarly, the LSB of the data word is transmitted immediately preceding the parity bit, or the stop bit if parity is not enabled. All necessary bit ordering is handled automatically by the module.
Page 711 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) received. If a NACK is received, the transmitter resends the data, assuming that the number of retries for that character, that is, the number of NACKs received, is less than or equal to the value in ET7816[TXTHRESHOLD]. Hardware supports odd or even parity.
Page 712: Receiver
Functional description NOTE When queuing a break character, it will be transmitted following the completion of the data value currently being shifted out from the shift register. This means that, if data is queued in the data buffer to be transmitted, the break character preempts that queued data.
Page 713 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) INTERNAL BUS BRFA4:0 SBR12:0 DATA BUFFER MODULE BAUDRATE VARIABLE 12-BIT RECEIVE CLOCK GENERATOR SHIFT REGISTER MSBF RECEIVE RXINV CONTROL SHIFT DIRECTION LOOPS RECEIVER RSRC SOURCE CONTROL PARITY WAKEUP LOGIC LOGIC From Transmitter DMA Requests IRQ / DMA ACTIVE EDGE LOGIC IRQ Requests...
Page 714 Functional description 38.5.2.3 Character reception During UART reception, the receive shift register shifts a frame in from the unsynchronized receiver input signal. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the UART receive buffer. The receive data buffer is accessible via the D and C3[T8] registers.
Page 715 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) Figure 38-3. Receiver data sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7 when C7816[ISO_7816E] is cleared/disabled and RT8, RT9 and RT10 when C7816[ISO_7816E] is set/enabled. The following table summarizes the results of the start bit verification samples.
Page 716 Functional description Table 38-5. Data bit recovery (continued) RT8, RT9, and RT10 samples Data bit determination Noise flag Note The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (S1[NF]) is set and the receiver assumes that the bit is a start bit (logic 0).
Page 717 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) Figure 38-4. Start bit search example 1 (C7816[ISO_7816E] = 0) In the following figure, verification sample at RT3 is high. In this example C7816[ISO_7816E] = 0. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
Page 718 Functional description Figure 38-6. Start bit search example 3 (C7816[ISO_7816E] = 0) The following figure shows the effect of noise early in the start bit time. In this example C7816[ISO_7816E] = 0. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag.
Page 719 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) Figure 38-8. Start bit search example 5 (C7816[ISO_7816E] = 0) In the following figure, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. In this example C7816[ISO_7816E] = 0. This sets the noise flag but does not reset the RT clock.
Page 720 Functional description 38.5.2.6 Receiving break characters The UART recognizes a break character when a start bit is followed by eight, nine, or ten logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has these effects on UART registers: •...
Page 721 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) STOP RECEIVER RT CLOCK DATA SAMPLES Figure 38-10. Slow data For an 8-bit data character, data sampling of the stop bit takes the receiver 154 RT cycles (9 bit times × 16 RT cycles + 10 RT cycles). With the misaligned character shown in the Figure 38-10, the receiver counts 154 RT...
Page 722 Functional description For an 8-bit data character, data sampling of the stop bit takes the receiver 154 RT cycles (9 bit times × 16 RT cycles + 10 RT cycles). With the misaligned character shown in the Figure 38-11, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 160 RT cycles (10 bit times ×...
Page 723 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) When C2[RWU] is 1 and S2[RWUID] is 0, the idle character that wakes the receiver does not set S1[IDLE] or the receive data register full flag, S1[RDRF]. The receiver wakes and waits for the first data character of the next message which is stored in the receive data buffer.
Page 724: Baud Rate Generation
Functional description Match address operation functions in the same way for both MA1 and MA2 registers. Note that the position of the address mark is the same as the Parity Bit when parity is enabled for 8 bit and 9 bit data formats. •...
Page 725 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) Table 38-8. Baud rates (example: module clock = 10.2 MHz) (continued) Bits Bits Receiver Transmitter Error Target Baud BRFD value rate BRFA clock (Hz) clock (Hz) (decimal) 10011 19/32=0.59375 614,689.3 38,418.08 38,400 0.047 00000 309,090.9 19,318.2 19,200 0.62...
Page 726: Data Format (Non Iso-7816)
Functional description Table 38-9. Baud rate fine adjust (continued) BRFA Baud Rate Fractional Divisor (BRFD) 1 0 1 1 0 22/32 = 0.6875 1 0 1 1 1 23/32 = 0.71875 1 1 0 0 0 24/32 = 0.75 1 1 0 0 1 25/32 = 0.78125 1 1 0 1 0 26/32 = 0.8125...
Page 727 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) 38.5.4.2 Nine-bit configuration When C1[M] is set and C4[M10] is cleared, the UART is configured for 9-bit data characters. If C1[PE] is enabled, the ninth bit is either C3[T8/R8] or the internally generated parity bit. This results in a frame consisting of a total of 11 bits. In the event that the ninth data bit is selected to be C3[T8], it will remain unchanged after transmission and can be used repeatedly without rewriting it, unless the value needs to be changed.
Page 728 Functional description 38.5.4.3.1 Eight-bit format with parity disabled The most significant bit can be used for address mark wakeup. ADDRESS MARK START START BIT 7 STOP BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 Figure 38-12.
Page 729: Single-Wire Operation
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) 38.5.4.3.5 Non-memory mapped tenth bit for parity The most significant memory-mapped bit can be used for address mark wakeup. ADDRESS MARK START START BIT 8 PARITY STOP BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6...
Page 730: Iso-7816/Smartcard Support
Functional description TXINV TRANSMITTER Tx pin output RECEIVER RXINV Figure 38-23. Loop operation (C1[LOOPS] = 1, C1[RSRC] = 0) Enable loop operation by setting C1[LOOPS] and clearing C1[RSRC]. Setting C1[LOOPS] disables the path from the unsynchronized receiver input signal to the receiver.
Page 731 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) provide configuration options that exceed the flexibility of options explicitly allowed by the 7816 specification. Failure to correctly configure the UART may result in unexpected behavior or incompatibility with the ISO-7816 specification. 38.5.7.1 Initial characters In ISO-7816 with T = 0 mode, the UART can be configured to use C7816[INIT] to detect the next valid initial character, referred to by the ISO-7816 specifically as a TS character.
Page 732 Functional description ISO 7816 FORMAT WITHOUT PARITY ERROR (T=0) NEXT PARITY START START STOP STOP BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 ISO 7816 FORMAT WITH PARITY ERROR (T=0) NACK NEXT PARITY ERROR START...
Page 733 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) Therefore, the software must program the transmit buffer with the next data to be transmitted and then enable C2[TE] and set C3[TXDIR], once the software has determined that the last character of the received block has been received. The UART detects that the last character of the transmit block has been sent when TL7816[TLEN] = 0 and four additional characters have been sent.
Page 734 Functional description The UART will automatically handle GT, CGT, and BGT such that the UART will not send a packet before the corresponding guard time expiring. Table 38-13. Wait and guard time calculations C7816[TTYPE] = 0 C7816[TTYPE] = 1 Reset value Parameter [ETU] [ETU]...
Page 735: Reset
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) shown; ADT = {AP7816a_T0[ADTI_H], AP7816a_T0[ADTI_L]}. This counter begins to count on detection of the TS character which is detected when IS7816[INITD] flag is set. Once the ATR process is completed, the ATD Counter must be disabled by writing 0 to AP7816x_T0 registers, in order to prevent the false occurrence of the ATD Duration Time interrupt IS7816[ATD].
Page 736: Rxedgif Description
System level interrupt sources However, RXEDGIF description also outlines additional details regarding the RXEDGIF interrupt because of its complexity of operation. Any of the UART interrupt requests listed in the table can be used to bring the CPU out of Wait mode. Table 38-14.
Page 737: Dma Operation
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) cycle, and then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input is seen as a logic 0 during one module clock cycle and then a logic 1 during the next cycle.
Page 738: Application Information
Application information 38.9 Application information This section describes the UART application information. 38.9.1 ISO-7816 initialization sequence This section outlines how to program the UART for ISO-7816 operation. Elements such as procedures to power up or power down the smartcard, and when to take those actions, are beyond the scope of this description.
Page 739: Initialization Sequence (Non Iso-7816)
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) At this time, the UART will start listening for an initial character. After being identified, it will automatically adjust S2[MSBF], C3[TXINV], and S2[RXINV]. The software must then receive and process an answer to reset. Upon processing the answer to reset, the software must write to set C2[RE] = 0 and C2[TE] = 0.
Page 740: Overrun (Or) Flag Implications
Application information 1. Configure the UART. a. Select a baud rate. Write this value to the UART baud registers (BDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is zero. Writing to the BDH has no effect without also writing to BDL.
Page 741: Overrun Nack Considerations
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) 38.9.3 Overrun (OR) flag implications To be flexible, the overrun flag (OR) operates slight differently depending on the mode of operation. There may be implications that need to be carefully considered. This section clarifies the behavior and the resulting implications. Regardless of mode, if a dataword is received while S1[OR] is set, S1[RDRF] and S1[IDLE] are blocked from asserting.
Page 742: Match Address Registers
Application information received, it is possible that the application code will read the data buffer such that sufficient room will be made to store the dataword that is being NACKed. Even if room has been made in the data buffer after the transmission of a NACK is completed, the received data will always be discarded as a result of an overflow and the ET7816[RXTHRESHOLD] value will be incremented by one.
Page 743 Chapter 38 Universal Asynchronous Receiver/Transmitter(UART) application code from previous versions is used, it must be reviewed and modified to take the following items into account. Depending on the application code, additional items that are not listed here may also need to be considered. 1.
Page 744 Application information KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 745: Chip-Specific Flexio Information
Chapter 39 FlexIO 39.1 Chip-specific FlexIO information 39.1.1 FlexIO Instantiation This section summarize the features and module configurations of FlexIO Amongst other features, the FlexIO module in this device supports: 1. Emulation in serial only communication protocols 39.1.2 FlexIO Trigger options FlexIO has a selectable trigger input source controlled by FlexIO_TIMCTLn[TRGSEL] (4-bit field) to use for starting the counter and/or reloading the counter.
Page 746: Introduction
Introduction Table 39-1. FlexIO Trigger Options (continued) FlexIO_TIMCTLn[TRGSEL] (4-bit Selected source field) 1011 Reserved 1100 RTC alarm 1101 RTC seconds 1110 LPTMR trigger 1111 Reserved 39.2 Introduction 39.2.1 Overview The FlexIO is a highly configurable module providing a wide range of functionality including: •...
Page 747: Block Diagram
Chapter 39 FlexIO • Array of 32-bit shift registers with transmit, receive and data match modes • Double buffered shifter operation for continuous data transfer • Shifter concatenation to support large transfer sizes • Automatic start/stop bit generation • Interrupt, DMA or polled transmit/receive operation •...
Page 748: Flexio Signal Descriptions
Memory Map and Registers 39.2.4 Modes of operation The FlexIO module supports the chip modes described in the following table. Table 39-2. Chip modes supported by the FlexIO module Chip mode FlexIO Operation Normal operation Stop/Wait Can continue operating provided the Doze Enable bit (CTRL[DOZEN]) is set and the FlexIO is using an external or internal clock source which remains operating during stop/wait modes.
Page 749 Chapter 39 FlexIO FLEXIO memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 39.3.11/ 4005_F084 Shifter Control N Register (FLEXIO_SHIFTCTL1) 0000_0000h 39.3.11/ 4005_F088 Shifter Control N Register (FLEXIO_SHIFTCTL2) 0000_0000h 39.3.11/ 4005_F08C Shifter Control N Register (FLEXIO_SHIFTCTL3) 0000_0000h 39.3.12/ 4005_F100...
Page 750: Version Id Register (Flexio_Verid)
Memory Map and Registers FLEXIO memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Shifter Buffer N Bit Byte Swapped Register 39.3.16/ 4005_F38C 0000_0000h (FLEXIO_SHIFTBUFBBS3) 39.3.17/ 4005_F400 Timer Control N Register (FLEXIO_TIMCTL0) 0000_0000h 39.3.17/ 4005_F404 Timer Control N Register (FLEXIO_TIMCTL1)
Page 751: Parameter Register (Flexio_Param)
Chapter 39 FlexIO FLEXIO_VERID field descriptions (continued) Field Description This read only field returns the major version number for the module specification. 23–16 Minor Version Number MINOR This read only field returns the minor version number for the module specification. FEATURE Feature Specification Number This read only field returns the feature set number.
Page 752: Flexio Control Register (Flexio_Ctrl)
Memory Map and Registers 39.3.3 FlexIO Control Register (FLEXIO_CTRL) Address: 4005_F000h base + 8h offset = 4005_F008h Reset Reset FLEXIO_CTRL field descriptions Field Description Doze Enable DOZEN Disables FlexIO operation in Doze modes. This field is ignored and the FlexIO always disabled in low- leakage stop modes.
Page 753: Shifter Status Register (Flexio_Shiftstat)
Chapter 39 FlexIO FLEXIO_CTRL field descriptions (continued) Field Description Software reset is disabled Software reset is enabled, all FlexIO registers except the Control Register are reset. FlexIO Enable FLEXEN FlexIO module is disabled. FlexIO module is enabled. 39.3.4 Shifter Status Register (FLEXIO_SHIFTSTAT) Address: 4005_F000h base + 10h offset = 4005_F010h Reset FLEXIO_SHIFTSTAT field descriptions...
Page 754: Shifter Error Register (Flexio_Shifterr)
Memory Map and Registers 39.3.5 Shifter Error Register (FLEXIO_SHIFTERR) Address: 4005_F000h base + 14h offset = 4005_F014h Reset FLEXIO_SHIFTERR field descriptions Field Description 31–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Shifter Error Flags The shifter error flag is set when one of the following events occurs: For SMOD=Receive, indicates Shifter was ready to store new data into SHIFTBUF before the previous...
Page 755: Shifter Status Interrupt Enable (Flexio_Shiftsien)
Chapter 39 FlexIO FLEXIO_TIMSTAT field descriptions Field Description 31–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Timer Status Flags The timer status flag sets depending on the timer mode, and can be cleared by writing logic one to the flag.
Page 756: Shifter Error Interrupt Enable (Flexio_Shifteien)
Memory Map and Registers 39.3.8 Shifter Error Interrupt Enable (FLEXIO_SHIFTEIEN) Address: 4005_F000h base + 24h offset = 4005_F024h SEIE Reset FLEXIO_SHIFTEIEN field descriptions Field Description 31–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. SEIE Shifter Error Interrupt Enable Enables interrupt generation when corresponding SEF is set.
Page 757: Shifter Status Dma Enable (Flexio_Shiftsden)
Chapter 39 FlexIO 39.3.10 Shifter Status DMA Enable (FLEXIO_SHIFTSDEN) Address: 4005_F000h base + 30h offset = 4005_F030h SSDE Reset FLEXIO_SHIFTSDEN field descriptions Field Description 31–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. SSDE Shifter Status DMA Enable Enables DMA request generation when corresponding SSF is set.
Page 758 Memory Map and Registers FLEXIO_SHIFTCTLn field descriptions Field Description 31–26 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 25–24 Timer Select TIMSEL Selects which Timer is used for controlling the logic/shift register and generating the Shift clock. Timer Polarity TIMPOL Shift on posedge of Shift clock...
Page 759: Shifter Configuration N Register (Flexio_Shiftcfgn)
Chapter 39 FlexIO 39.3.12 Shifter Configuration N Register (FLEXIO_SHIFTCFGn) Address: 4005_F000h base + 100h offset + (4d × i), where i=0d to 3d Reset SSTOP SSTART Reset FLEXIO_SHIFTCFGn field descriptions Field Description 31–21 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 20–16 This field is reserved.
Page 760: Shifter Buffer N Register (Flexio_Shiftbufn)
Memory Map and Registers FLEXIO_SHIFTCFGn field descriptions (continued) Field Description 3–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. SSTART Shifter Start bit For SMOD=Transmit, this field allows automatic start bit insertion if the selected timer has also enabled a start bit.
Page 761: Shifter Buffer N Bit Swapped Register (Flexio_Shiftbufbisn)
Chapter 39 FlexIO 39.3.14 Shifter Buffer N Bit Swapped Register (FLEXIO_SHIFTBUFBISn) Address: 4005_F000h base + 280h offset + (4d × i), where i=0d to 3d SHIFTBUFBIS Reset FLEXIO_SHIFTBUFBISn field descriptions Field Description SHIFTBUFBIS Shift Buffer Alias to SHIFTBUF register, except reads/writes to this register are bit swapped. Reads return SHIFTBUF[0:31].
Page 762: Shifter Buffer N Bit Byte Swapped Register (Flexio_Shiftbufbbsn)
Memory Map and Registers 39.3.16 Shifter Buffer N Bit Byte Swapped Register (FLEXIO_SHIFTBUFBBSn) Address: 4005_F000h base + 380h offset + (4d × i), where i=0d to 3d SHIFTBUFBBS Reset FLEXIO_SHIFTBUFBBSn field descriptions Field Description SHIFTBUFBBS Shift Buffer Alias to SHIFTBUF register, except reads/writes to this register are bit swapped within each byte. Reads return { SHIFTBUF[24:31], SHIFTBUF[16:23], SHIFTBUF[8:15], SHIFTBUF[0:7] }.
Page 763 Chapter 39 FlexIO FLEXIO_TIMCTLn field descriptions (continued) Field Description • When TRGSRC = 1, the valid values for N will depend on PIN, TIMER, SHIFTER fields in the FLEXIO_PARAM register. • When TRGSRC = 0, the valid values for N will depend on TRIGGER field in FLEXIO_PARAM register.
Page 764: Timer Configuration N Register (Flexio_Timcfgn)
Memory Map and Registers FLEXIO_TIMCTLn field descriptions (continued) Field Description Dual 8-bit counters baud/bit mode. Dual 8-bit counters PWM mode. Single 16-bit counter mode. 39.3.18 Timer Configuration N Register (FLEXIO_TIMCFGn) The options to enable or disable the timer using the Timer N-1 enable or disable are reserved when N is evenly divisible by 4 (eg: Timer 0).
Page 765 Chapter 39 FlexIO FLEXIO_TIMCFGn field descriptions (continued) Field Description Decrement counter on Pin input (both edges), Shift clock equals Pin input. Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. This field is reserved. Reserved This read-only field is reserved and always has the value 0. 18–16 Timer Reset TIMRST...
Page 766: Timer Compare N Register (Flexio_Timcmpn)
Memory Map and Registers FLEXIO_TIMCFGn field descriptions (continued) Field Description 5–4 Timer Stop Bit TSTOP The stop bit can be added on a timer compare (between each word) or on a timer disable. When stop bit is enabled, configured shifters will output the contents of the stop bit when the timer is disabled. When stop bit is enabled on timer disable, the timer remains disabled until the next rising edge of the shift clock.
Page 767: Functional Description
Chapter 39 FlexIO FLEXIO_TIMCMPn field descriptions (continued) Field Description trigger input, the compare register is used to set the number of bits in each word equal to (CMP[15:0] + 1) / 2. 39.4 Functional description 39.4.1 Shifter operation Shifters are responsible for buffering and shifting data into or out of the FlexIO. The timing of shift, load and store events are controlled by the Timer assigned to the Shifter via the SHIFTCTL[TIMSEL] register.
Page 768 Functional description The Shifter Status Flag (SHIFTSTAT[SSF]) and any enabled interrupts or DMA requests will set when data has been loaded from the SHIFTBUF register into the Shifter or when the Shifter is initially configured into Transmit mode. The flag will clear when new data has been written into the SHIFTBUF register.
Page 769: Timer Operation
Chapter 39 FlexIO The Shifter Error Flag (SHIFTERR[SEF]) and any enabled interrupts will set when an attempt to store matched data into a full SHIFTBUF register occurs (buffer overrun) or when a mismatch occurs on a start/stop bit check. The flag can be cleared by writing it with logic 1.
Page 770 Functional description The Timer Configuration Register (TIMCFGn) should be configured before setting the Timer Mode (TIMOD). Once the TIMOD is configured for the desired mode, when the condition configured by timer enable (TIMENA) is detected then the following events occur. •...
Page 771: Pin Operation
Chapter 39 FlexIO • Transmit shifters controlled by this timer will output their stop bit value (if configured by SSTOP). • Receive shifters controlled by this timer will store the contents of the shift register in their shift buffer, as configured by SSTOP. •...
Page 772: Application Information
Application Information When configuring a pin as an input (this includes a timer trigger configured as a pin input), the input signal is first synchronized to the FlexIO clock before the signal is used by a timer or shifter. This introduces a small latency of between 0.5 to 1.5 FlexIO clock cycles when using an external pin input to generate an output or control a shifter.
Page 773: Uart Receive
Chapter 39 FlexIO number of bits to transmit). Note that when performing byte writes to SHIFTBUFn (or SHIFTBUFBIS for transmitting MSB first), the rest of the register remains unaltered allowing an address mark bit or additional stop bit to remain undisturbed. FlexIO does not support automatic insertion of parity bits.
Page 774 Application Information FlexIO does not support automatic verification of parity bits. Table 39-4. UART Receiver Configuration Register Value Comments SHIFTCFGn 0x0000_0032 Configure start bit of 0 and stop bit of 1. SHIFTCTLn 0x0080_0001 Configure receive using Timer 0 on negedge of clock with input data on Pin 0.
Page 775: Spi Master
Chapter 39 FlexIO Table 39-5. UART Receiver with RTS Configuration (continued) Register Value Comments to received data with TIMOUT=0x2 and TIMRST=0x4. TIMCTLn 0x03C0_0081 Configure dual 8-bit counter using inverted Pin 0 input. Trigger is internal using inverted Pin 1 input. TIMCMP(n+1) 0x0000_FFFF Never compare.
Page 776 Application Information Table 39-6. SPI Master (CPHA=0) Configuration (continued) Register Value Comments SHIFTCTL(n+1) 0x0000_0101 Configure receive using Timer 0 on posedge of clock with input data on Pin TIMCMPn 0x0000_3F01 Configure 32-bit transfer with baud rate of divide by 4 of the FlexIO clock. Set TIMCMP[15:8] = (number of bits x 2) - 1.
Page 777: Spi Slave
Chapter 39 FlexIO Table 39-7. SPI Master (CPHA=1) Configuration (continued) Register Value Comments Set TIMCMP[7:0] = (baud rate divider / 2) - 1. TIMCFGn 0x0100_2222 Configure start bit, stop bit, enable on trigger high and disable on compare, initial clock state is logic 0. Set PINPOL to invert the output shift clock.
Page 778 Application Information Table 39-8. SPI Slave (CPHA=0) Configuration Register Value Comments SHIFTCFGn 0x0000_0000 Start and stop bit disabled. SHIFTCTLn 0x0083_0002 Configure transmit using Timer 0 on falling edge of shift clock with output data on Pin 0. SHIFTCFG(n+1) 0x0000_0000 Start and stop bit disabled. SHIFTCTL(n+1) 0x0000_0101 Configure receive using Timer 0 on...
Page 779: I2C Master
Chapter 39 FlexIO Table 39-9. SPI Slave (CPHA=1) Configuration (continued) Register Value Comments TIMCTLn 0x06C0_0203 Configure 16-bit counter using Pin 2 input (shift clock), with Pin 3 input (slave select) as the inverted trigger. SHIFTBUFn Data to transmit Transmit data can be written to SHIFTBUF, use the Shifter Status Flag to indicate when data can be written using interrupt or DMA request.
Page 780 Application Information The receive shift register will assert an error interrupt if a NACK is detected, but software is responsible for generating the STOP or repeated START condition. If a NACK is detected during master-transmit, the interrupt routine should immediately write the transmit shifter register with 0x00 (if generating STOP) or 0xFF (if generating repeated START).
Page 781: I2S Master
Chapter 39 FlexIO Table 39-10. I2C Master Configuration (continued) Register Value Comments SHIFTBUFn Data to transmit Transmit data can be written to SHIFTBUFBBS[7:0], use the Shifter Status Flag to indicate when data can be written using interrupt or DMA request. SHIFTBUF(n+1) Data to receive Received data can be read from...
Page 782: I2S Slave
Application Information Table 39-11. I2S Master Configuration (continued) Register Value Comments TIMCFGn 0x0000_0202 Configure start bit, enable on trigger high and never disable. Initial clock state is logic 1. TIMCTLn 0x01C3_0201 Configure dual 8-bit counter using Pin 2 output (bit clock), with Shifter 0 flag as the inverted trigger.
Page 783 Chapter 39 FlexIO Table 39-12. I2S Slave Configuration Register Value Comments SHIFTCFGn 0x0000_0000 Start and stop bit disabled. SHIFTCTLn 0x0103_0002 Configure transmit using Timer 1 on rising edge of shift clock with output data on Pin 0. SHIFTCFG(n+1) 0x0000_0000 Start and stop bit disabled. SHIFTCTL(n+1) 0x0180_0101 Configure receive using Timer 1 on...
Page 784 Application Information KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 785: Synchronous Audio Interface (Sai)
Chapter 40 Synchronous Audio Interface (SAI) 40.1 Chip-specific I2S information 40.1.1 Instantiation information This device contains one I S module. As configured on the device, module features include: • TX data lines: 1 • RX data lines: 1 • FIFO size (words): 1 •...
Page 786 Chip-specific I2S information 40.1.3.1 Audio Master Clock The audio master clock (MCLK) is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. The audio master clock can also be output to or input from a pin. The transmitter and receiver have the same audio master clock inputs.
Page 787: I2S/Sai Operation In Low Power Modes
Chapter 40 Synchronous Audio Interface (SAI) The transmitter and receiver can independently select between the bus clock and the audio master clock to generate the bit clock. The module's Clocking Mode field of the Transmit Configuration 2 Register and Receive Configuration 2 Register (TCR2[MSEL] and RCR2[MSEL]) selects the master clock.
Page 788: Introduction
Introduction When operating from an internally generated bit clock or Audio Master Clock that is disabled in stop modes: In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter is disabled after completing the current transmit frame, and, if the Receiver Stop Enable (RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive frame.
Page 789: Block Diagram
Chapter 40 Synchronous Audio Interface (SAI) 40.2.2 Block diagram The following block diagram also shows the module clocks. Write Read Shift FIFO FIFO FIFO SAI_TX_DATA Register Control Control SAI_TX_BCLK Clock Clock Frame Control Bit Clock Sync SAI_TX_SYNC Registers Generation Control Transmitter Audio Synchronous Mode...
Page 790: External Signals
External signals In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter is disabled after completing the current transmit frame, and, if the Receiver Stop Enable (RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive frame.
Page 791: Memory Map And Register Definition
Chapter 40 Synchronous Audio Interface (SAI) Name Function externally generated and an output generated synchronously by the bit clock when internally generated. SAI_RX_DATA Receive Data. The receive data is sampled synchronously by the bit clock. SAI_MCLK Audio Master Clock. The master clock is an input when externally generated and an output when internally generated.
Page 792: Sai Transmit Control Register (I2Sx_Tcsr)
Memory map and register definition 40.4.1 SAI Transmit Control Register (I2Sx_TCSR) Address: 4002_F000h base + 0h offset = 4002_F000h Reset WSIE SEIE FEIE FWIE Reset I2Sx_TCSR field descriptions Field Description Transmitter Enable Enables/disables the transmitter. When software clears this field, the transmitter remains enabled, and this bit remains set, until the end of the current frame.
Page 793 Chapter 40 Synchronous Audio Interface (SAI) I2Sx_TCSR field descriptions (continued) Field Description Enables/disables transmitter operation in Debug mode. The transmit bit clock is not affected by debug mode. Transmitter is disabled in Debug mode, after completing the current frame. Transmitter is enabled in Debug mode. Bit Clock Enable Enables the transmit bit clock, separately from the TE.
Page 794 Memory map and register definition I2Sx_TCSR field descriptions (continued) Field Description FIFO Warning Flag Indicates that an enabled transmit FIFO is empty. No enabled transmit FIFO is empty. Enabled transmit FIFO is empty. This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–13 This field is reserved.
Page 795: Sai Transmit Configuration 2 Register (I2Sx_Tcr2)
Chapter 40 Synchronous Audio Interface (SAI) 40.4.2 SAI Transmit Configuration 2 Register (I2Sx_TCR2) This register must not be altered when TCSR[TE] is set. Address: 4002_F000h base + 8h offset = 4002_F008h SYNC MSEL Reset Reset I2Sx_TCR2 field descriptions Field Description 31–30 Synchronous Mode SYNC...
Page 796: Sai Transmit Configuration 3 Register (I2Sx_Tcr3)
Memory map and register definition I2Sx_TCR2 field descriptions (continued) Field Description 27–26 MCLK Select MSEL Selects the audio Master Clock option used to generate an internally generated bit clock. This field has no effect when configured for an externally generated bit clock. NOTE: Depending on the device, some Master Clock options might not be available.
Page 797: Sai Transmit Configuration 4 Register (I2Sx_Tcr4)
Chapter 40 Synchronous Audio Interface (SAI) I2Sx_TCR3 field descriptions Field Description 31–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 23–17 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Transmit Channel Enable Enables the corresponding data channel for transmit operation.
Page 798 Memory map and register definition I2Sx_TCR4 field descriptions (continued) Field Description FIFO Continue on Error FCONT Configures when the SAI will continue transmitting after a FIFO error has been detected. On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
Page 799: Sai Transmit Configuration 5 Register (I2Sx_Tcr5)
Chapter 40 Synchronous Audio Interface (SAI) I2Sx_TCR4 field descriptions (continued) Field Description When set, and the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear. Internal frame sync is generated continuously. Internal frame sync is generated when the FIFO warning flag is clear.
Page 800: Sai Transmit Data Register (I2Sx_Tdrn)
Memory map and register definition I2Sx_TCR5 field descriptions (continued) Field Description 12–8 First Bit Shifted Configures the bit index for the first bit transmitted for each word in the frame. If configured for MSB First, the index of the next bit transmitted is one less than the current bit transmitted. If configured for LSB First, the index of the next bit transmitted is one more than the current bit transmitted.
Page 801: Sai Receive Control Register (I2Sx_Rcsr)
Chapter 40 Synchronous Audio Interface (SAI) I2Sx_TMR field descriptions Field Description 31–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Transmit Word Mask Configures whether the transmit word is masked (transmit data pin tristated and transmit data not read from FIFO) for the corresponding word in the frame.
Page 802 Memory map and register definition I2Sx_RCSR field descriptions (continued) Field Description Enables/disables the receiver. When software clears this field, the receiver remains enabled, and this bit remains set, until the end of the current frame. Receiver is disabled. Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. Stop Enable STOPE Configures receiver operation in Stop mode.
Page 803 Chapter 40 Synchronous Audio Interface (SAI) I2Sx_RCSR field descriptions (continued) Field Description Sync Error Flag Indicates that an error in the externally-generated frame sync has been detected. Write a logic 1 to this field to clear this flag. Sync error not detected. Frame sync error detected.
Page 804: Sai Receive Configuration 2 Register (I2Sx_Rcr2)
Memory map and register definition I2Sx_RCSR field descriptions (continued) Field Description 4–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. FIFO Warning DMA Enable FWDE Enables/disables DMA requests. Disables the DMA request. Enables the DMA request.
Page 805 Chapter 40 Synchronous Audio Interface (SAI) I2Sx_RCR2 field descriptions (continued) Field Description Use the normal bit clock source. Swap the bit clock source. Bit Clock Input When this field is set and using an internally generated bit clock in either synchronous or asynchronous mode, the bit clock actually used by the receiver is delayed by the pad output delay (the receiver is clocked by the pad input as if the clock was externally generated).
Page 806: Sai Receive Configuration 3 Register (I2Sx_Rcr3)
Memory map and register definition 40.4.10 SAI Receive Configuration 3 Register (I2Sx_RCR3) Address: 4002_F000h base + 8Ch offset = 4002_F08Ch Reset Reset I2Sx_RCR3 field descriptions Field Description 31–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 23–17 This field is reserved.
Page 807: Sai Receive Configuration 4 Register (I2Sx_Rcr4)
Chapter 40 Synchronous Audio Interface (SAI) 40.4.11 SAI Receive Configuration 4 Register (I2Sx_RCR4) This register must not be altered when RCSR[RE] is set. Address: 4002_F000h base + 90h offset = 4002_F090h FPACK FRSZ Reset SYWD Reset I2Sx_RCR4 field descriptions Field Description 31–29 This field is reserved.
Page 808 Memory map and register definition I2Sx_RCR4 field descriptions (continued) Field Description Frame Size FRSZ Configures the number of words in each frame. The value written must be one less than the number of words in the frame. For example, write 0 for one word per frame. The maximum supported frame size is 2 words.
Page 809: Sai Receive Configuration 5 Register (I2Sx_Rcr5)
Chapter 40 Synchronous Audio Interface (SAI) 40.4.12 SAI Receive Configuration 5 Register (I2Sx_RCR5) This register must not be altered when RCSR[RE] is set. Address: 4002_F000h base + 94h offset = 4002_F094h Reset I2Sx_RCR5 field descriptions Field Description 31–29 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 810: Sai Receive Mask Register (I2Sx_Rmr)
Memory map and register definition I2Sx_RDRn field descriptions Field Description Receive Data Register The corresponding RCR3[RCE] bit must be set before accessing the channel's receive data register. Reads from this register when the receive FIFO is not empty will return the data from the top of the receive FIFO.
Page 811: Sai Mclk Control Register (I2Sx_Mcr)
Chapter 40 Synchronous Audio Interface (SAI) 40.4.15 SAI MCLK Control Register (I2Sx_MCR) The MCLK Control Register (MCR) controls the clock source and direction of the audio master clock. Address: 4002_F000h base + 100h offset = 4002_F100h MICS Reset Reset I2Sx_MCR field descriptions Field Description Divider Update Flag...
Page 812: Functional Description
Functional description 40.5 Functional description This section provides a complete functional description of the block. 40.5.1 SAI clocking The SAI clocks include: • The audio master clock • The bit clock • The bus clock 40.5.1.1 Audio master clock The audio master clock is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock.
Page 813 Chapter 40 Synchronous Audio Interface (SAI) CLKGEN MCLK (other SAIs) MCLK_OUT BCLK_OUT PLL_OUT Fractional ALT_CLK Clock MCLK EXTAL Clock SYS_CLK BCLK Divider MCLK_IN BUS_CLK Divider BCLK_IN SAI_CLKMODE SAI_BCD SAI_MOE SAI_FRACT/SAI_DIVIDE SAI_MICS Figure 40-2. SAI master clock generation The MCLK fractional clock divider uses both clock edges from the input clock to generate a divided down clock that will approximate the output frequency, but without creating any new clock edges.
Page 814: Sai Resets
Functional description 40.5.1.3 Bus clock The bus clock is used by the control and configuration registers and to generate synchronous interrupts and DMA requests. NOTE Although there is no specific minimum bus clock frequency specified, the bus clock frequency must be fast enough (relative to the bit clock frequency) to ensure that the FIFOs can be serviced, without generating either a transmitter FIFO underrun or receiver FIFO overflow condition.
Page 815: Synchronous Modes
Chapter 40 Synchronous Audio Interface (SAI) 40.5.3 Synchronous modes The SAI transmitter and receiver can operate synchronously to each other. 40.5.3.1 Synchronous mode The SAI transmitter and receiver can be configured to operate with synchronous bit clock and frame sync. If the transmitter bit clock and frame sync are to be used by both the transmitter and receiver: •...
Page 816: Data Fifo
Functional description The frame sync signal is used to indicate the start of each frame. A valid frame sync requires a rising edge (if active high) or falling edge (if active low) to be detected and the transmitter or receiver cannot be busy with a previous frame. A valid frame sync is also ignored (slave mode) or not generated (master mode) for the first four bit clock cycles after enabling the transmitter or receiver.
Page 817 Chapter 40 Synchronous Audio Interface (SAI) Figure 40-3. SAI first bit shifted, LSB first Figure 40-4. SAI first bit shifted, MSB first 40.5.5.2 FIFO pointers When writing to a TDR, the WFP of the corresponding TFR increments after each valid write.
Page 818 Functional description When reading an RDR, the RFP of the corresponding RFR increments after each valid read. The SAI supports 8-bit, 16-bit and 32-bit reads from the RDR and the FIFO pointer will increment after each individual read. Note that 8-bit reads should only be used when receiving up to 8-bit data and 16-bit reads should only be used when receiving up to 16- bit data.
Page 819: Word Mask Register
Chapter 40 Synchronous Audio Interface (SAI) 40.5.6 Word mask register The SAI transmitter and receiver each contain a word mask register, namely TMR and RMR, that can be used to mask any word in the frame. Because the word mask register is double buffered, software can update it before the end of each frame to mask a particular word in the next frame.
Page 820 Functional description When TCR4[FCONT] is set, the FIFO will continue transmitting data following an underflow without software intervention. To ensure that data is transmitted in the correct order, the transmitter will continue from the same word number in the frame that caused the FIFO to underflow, but only after new data has been written to the transmit FIFO.
Page 821: Chip-Specific Gpio Information
Chapter 41 General-Purpose Input/Output (GPIO) 41.1 Chip-specific GPIO information 41.1.1 GPIO instantiation information The device includes a number of pins, PTB0, PTB1, PTD6,PTD7, PTC3, and PTC4 with high current drive capability. These pins can be used to drive LED or power MOSFET directly.
Page 822: Introduction
Introduction 41.2 Introduction The GPIO registers support 8-bit, 16-bit or 32-bit accesses. The GPIO data direction and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function. The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function, provided the corresponding Port Control and Interrupt module for that pin is enabled.
Page 823: General-Purpose Input/Output (Gpio)
Chapter 41 General-Purpose Input/Output (GPIO) 41.2.3 GPIO signal descriptions Table 41-2. GPIO signal descriptions GPIO signal descriptions Description PORTA31–PORTA0 General-purpose input/output PORTB31–PORTB0 General-purpose input/output PORTC31–PORTC0 General-purpose input/output PORTD31–PORTD0 General-purpose input/output PORTE31–PORTE0 General-purpose input/output NOTE Not all pins within each port are implemented on each device. See the chapter on signal multiplexing for the number of GPIO ports available in the device.
Page 824: Memory Map And Register Definition
Memory map and register definition 41.3 Memory map and register definition Any read or write access to the GPIO memory space that is outside the valid memory map results in a bus error. GPIO memory map Absolute Width Section/ address Register name Access Reset value...
Page 825: Port Data Output Register (Gpiox_Pdor)
Chapter 41 General-Purpose Input/Output (GPIO) GPIO memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 400F_F0C4 Port Set Output Register (GPIOD_PSOR) (always 0000_0000h 41.3.2/826 reads 0) 400F_F0C8 Port Clear Output Register (GPIOD_PCOR) (always 0000_0000h 41.3.3/826 reads 0)
Page 826: Port Set Output Register (Gpiox_Psor)
Memory map and register definition GPIOx_PDOR field descriptions Field Description Port Data Output Register bits for unbonded pins return a undefined value when read. Logic level 0 is driven on pin, provided pin is configured for general-purpose output. Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 41.3.2 Port Set Output Register (GPIOx_PSOR) This register configures whether to set the fields of the PDOR.
Page 827: Port Toggle Output Register (Gpiox_Ptor)
Chapter 41 General-Purpose Input/Output (GPIO) GPIOx_PCOR field descriptions (continued) Field Description Writing to this register will update the contents of the corresponding bit in the Port Data Output Register (PDOR) as follows: Corresponding bit in PDORn does not change. Corresponding bit in PDORn is cleared to logic 0. 41.3.4 Port Toggle Output Register (GPIOx_PTOR) Address: Base address + Ch offset PTTO...
Page 828: Port Data Direction Register (Gpiox_Pddr)
Functional description GPIOx_PDIR field descriptions Field Description Port Data Input Reads 0 at the unimplemented pins for a particular device. Pins that are not configured for a digital function read 0. If the Port Control and Interrupt module is disabled, then the corresponding bit in PDIR does not update.
Page 829 Chapter 41 General-Purpose Input/Output (GPIO) 41.4.2 General-purpose output The logic state of each pin can be controlled via the port data output registers and port data direction registers, provided the pin is configured for the GPIO function. The following table depicts the conditions for a pin to be configured as input/output. Then A pin is configured for the GPIO function and the The pin is configured as an input.
Page 830 Functional description KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 831: Bit Manipulation Engine (Bme)
Chapter 42 Bit Manipulation Engine (BME) 42.1 Introduction The Bit Manipulation Engine (BME) provides hardware support for atomic read-modify- write memory operations to the peripheral address space in Cortex-M0+ based microcontrollers. This architectural capability is also known as "decorated storage" as it defines a mechanism for providing additional semantics for load and store operations to memory- mapped peripherals beyond just the reading and writing of data values to the addressed memory locations.
Page 832: Overview
Introduction 42.1.1 Overview The following figure is a generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers. Cortex-M0+ Core CM0+ Core Platform Fetch NVIC SHFT LD/ST MTB Port AHB Bus IO Port PRAM Array GPIO AXBS...
Page 833: Modes Of Operation
Chapter 42 Bit Manipulation Engine (BME) • Additional access semantics encoded into the reference address • Resides between a crossbar switch slave port and a peripheral bridge bus controller • Two-stage pipeline design matching the AHB system bus protocol • Combinationally passes non-decorated accesses to peripheral bridge bus controller •...
Page 834: Bme Decorated Stores
Functional description Recall the combination of the basic load and store instructions of the Cortex-M instruction set architecture (v6M, v7M) plus the concept of decorated storage provided by the BME, the resulting implementation provides a robust and efficient read-modify-write capability to this class of ultra low-end microcontrollers. The resulting architectural capability defined by this core platform function is targeted at the manipulation of n-bit fields in peripheral registers and is consistent with I/O hardware addressing in the Embedded C standard.
Page 835 Chapter 42 Bit Manipulation Engine (BME) CYCLE RULER hclk BME AHB Input Bus mx_haddr next 5..v_wxyz mx_hattr next mx_hwrite next mx_hwdata wdata mx_hrdata mx_hready BME AHB Output Bus sx_haddr 400v_wxyz next 400v_wxyz sx_hattr next sx_hwrite next sx_hwdata wdata bfi rdata sx_hrdata rdata sx_hready...
Page 836 Functional description 42.3.1.1 Decorated store logical AND (AND) This command performs an atomic read-modify-write of the referenced memory location. 1. First, the location is read; 2. It is then modified by performing a logical AND operation using the write data operand sourced for the system bus cycle 3.
Page 837 Chapter 42 Bit Manipulation Engine (BME) Table 42-1. Cycle definitions of decorated store: logical AND (continued) Pipeline stage Cycle master_wt to slave_rd; Capture address, attributes BME AHB_dp <previous> Perform memory read; Form Perform write sending (rdata & wdata) and capture registered data to memory destination data in register 42.3.1.2 Decorated store logical OR (OR)
Page 838 Functional description Table 42-2. Cycle definitions of decorated store: logical OR Pipeline stage Cycle BME AHB_ap Forward addr to memory; Recirculate captured addr + <next> Decode decoration; Convert attr to memory as slave_wt master_wt to slave_rd; Capture address, attributes BME AHB_dp <previous>...
Page 839 Chapter 42 Bit Manipulation Engine (BME) Table 42-3. Cycle definitions of decorated store: logical XOR Pipeline Stage Cycle BME AHB_ap Forward addr to memory; Recirculate captured addr + <next> Decode decoration; Convert attr to memory as slave_wt master_wt to slave_rd; Capture address, attributes BME AHB_dp <previous>...
Page 840 Functional description The decorated BFI write operation is defined in the following pseudo-code as: iobfi<sz>(accessAddress, wdata) // decorated bit field insert mem[accessAddress & 0xE007FFFF, size] // memory read mask = ((1 << (w+1)) - 1) << b // generate bit mask &...
Page 841: Bme Decorated Loads
Chapter 42 Bit Manipulation Engine (BME) 42.3.2 BME decorated loads The functions supported by the BME's decorated loads include two single-bit load-and- {set, clear} operators plus unsigned bit field extracts. For the two load-and-{set, clear} operations, BME converts a single decorated AHB load transaction into a two-cycle atomic read-modify-write sequence, where the combined read-modify operations are performed in the first AHB data phase, and then the write is performed in the second AHB data phase as the original read data is returned to the...
Page 842 Functional description CYCLE RULER hclk BME AHB Input Bus mx_haddr 4c.v_wxyz next mx_hattr next mx_hwrite next mx_hwdata mx_hrdata orig_1bit mx_hready BME AHB Output Bus sx_haddr 400v_wxyz 400v_wxyz next sx_hattr next sx_hwrite next sx_hwdata rdata + 1bit sx_hrdata rdata sx_hready BME States + Datapath control_state_dp1 control_state_dp2 reg_addr_data_dp...
Page 843 Chapter 42 Bit Manipulation Engine (BME) NOTE Any wait states inserted by the slave device are simply passed through the BME back to the master input bus, stalling the AHB transaction cycle for cycle. A generic timing diagram of a decorated load showing an unsigned peripheral bit field operation is shown in the following figure.
Page 844 Functional description • Cycle x+1, 1st AHB data phase: A bit mask is generated based on the starting bit position and the field width; the mask is AND'ed with the memory read data to isolate the bit field; the resulting data is captured in a data register; the input bus cycle is stalled •...
Page 845 Chapter 42 Bit Manipulation Engine (BME) The cycle-by-cycle BME operations are detailed in the following table. Table 42-5. Cycle definitions of decorated load: load-and-clear 1 bit Pipeline Stage Cycle BME AHB_ap Forward addr to memory; Recirculate captured addr + <next> Decode decoration;...
Page 846 Functional description tmp | mask // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write The cycle-by-cycle BME operations are detailed in the following table. Table 42-6. Cycle definitions of decorated load: load-and-set 1-bit Pipeline Stage Cycle BME AHB_ap Forward addr to memory;...
Page 847: Additional Details On Decorated Addresses And Gpio Accesses
Chapter 42 Bit Manipulation Engine (BME) offset into the space based at 0x4000_0000 for peripheral. The "-" indicates an address bit "don't care". Note, unlike the other decorated load operations, UBFX uses addr[19] as the least significant bit in the "w" specifier and not as an address bit. The decorated unsigned bit field extract read operation is defined in the following pseudo-code as: rdata =...
Page 848: Application Information
Application information As a result, undecorated GPIO references and decorated AND, OR, XOR, LAC1 and LAS1 operations can use the standard 0x400F_F000 base address, while decorated BFI and UBFX operations must use the alternate 0x4000_F000 base address. Another implementation can simply use 0x400F_F000 as the base address for all undecorated GPIO accesses and 0x4000_F000 as the base address for all decorated accesses.
Page 849 Chapter 42 Bit Manipulation Engine (BME) #define IOORW(ADDR,WDATA) __asm("ldr r3, =(1<<27);" "orr r3, %[addr];" "mov r2, %[wdata];" "str r2, [r3];" :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOORH(ADDR,WDATA) __asm("ldr r3, =(1<<27);" "orr r3, %[addr];" "mov r2, %[wdata];" "strh r2, [r3];"...
Page 850 Application information KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 851: Micro Trace Buffer (Mtb)
Chapter 43 Micro Trace Buffer (MTB) 43.1 Introduction Microcontrollers using the Cortex-M0+ processor core include support for a CoreSight Micro Trace Buffer to provide program trace capabilities. The proper name for this function is the CoreSight Micro Trace Buffer for the Cortex- M0+ Processor;...
Page 852 Introduction Cortex-M0+ Core CM0+ Core Platform Fetch NVIC SHFT LD/ST AHB Bus IO Port MTB Port PRAM Array GPIO Slave Peripherals Alt-Master PBRIDGE DMA_4ch AXBS Array Figure 43-1. Generic Cortex-M0+ core platform block diagram As shown in the block diagram, the platform RAM (PRAM) controller connects to two input buses: •...
Page 853 Chapter 43 Micro Trace Buffer (MTB) The following figure shows how the execution trace information is stored in memory as a sequence of packets. Nth destination address Odd word address Nth source address Even word address Incrementing SRAM memory address Start bit 2nd destination address 2nd source address...
Page 854: Features
Introduction • Destination address field set to bits[31:1] of the EXC_RETURN value. See the ARM v6-M Architecture Reference Manual. • The A-bit set to 0. • The second packet has the: • Source address field set to bits[31:1] of the EXC_RETURN value. •...
Page 855: Modes Of Operation
Chapter 43 Micro Trace Buffer (MTB) • Two DWT comparators (addresses or address + data) provide programmable start/ stop recording • CoreSight compliant debug functionality 43.1.3 Modes of operation The MTB_RAM and MTB_DWT functions do not support any special modes of operation.
Page 856: Memory Map And Register Definition
Memory map and register definition In addition, there are two signals formed by the MTB_DWT module and driven to the MTB_RAM controller: TSTART (trace start) and TSTOP (trace stop). These signals can be configured using the trace watchpoints to define programmable addresses and data values to affect the program trace recording state.
Page 857 Chapter 43 Micro Trace Buffer (MTB) MTB memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 43.3.1.6/ F000_0FA0 Claim TAG Set Register (MTB_TAGSET) 0000_0000h 43.3.1.7/ F000_0FA4 Claim TAG Clear Register (MTB_TAGCLEAR) 0000_0000h 43.3.1.8/ F000_0FB0 Lock Access Register (MTB_LOCKACCESS) 0000_0000h 43.3.1.9/...
Page 858 Memory map and register definition 43.3.1.1 MTB Position Register (MTB_POSITION) The MTB_POSITION register contains the Trace Write Address Pointer and Wrap fields. This register can be modified by the explicit programming model writes. It is also automatically updated by the MTB hardware when trace packets are being recorded. The base address of the system RAM in the memory map dictates special consideration for the placement of the MTB.
Page 859 Chapter 43 Micro Trace Buffer (MTB) * Notes: • x = Undefined at reset. MTB_POSITION field descriptions Field Description 31–3 Trace Packet Address Pointer[28:0] POINTER Because a packet consists of two words, the POINTER field is the address of the first word of a packet. This field contains bits[31:3] of the RAM address where the next trace packet is written.
Page 860 Memory map and register definition NOTE The format of this mask field is different than MTBDWT_MASKn[MASK]. Address: F000_0000h base + 4h offset = F000_0004h Reset MASK Reset * Notes: • x = Undefined at reset. MTB_MASTER field descriptions Field Description Main Trace Enable When this field is 1, trace data is written into the RAM memory location addressed by MTB_POSITION[POINTER].
Page 861 Chapter 43 Micro Trace Buffer (MTB) MTB_MASTER field descriptions (continued) Field Description Special Function Register Write Privilege SFRWPRIV If this field is 0, then user or privileged AHB read and write accesses to the MTB_RAM Special Function Registers (programming model) are permitted. If this field is 1, then only privileged write accesses are permitted;...
Page 862 Memory map and register definition Address: F000_0000h base + 8h offset = F000_0008h WATERMARK Reset WATERMARK Reset * Notes: • x = Undefined at reset. MTB_FLOW field descriptions Field Description 31–3 WATERMARK[28:0] WATERMARK This field contains an address in the same format as the MTB_POSITION[POINTER] field. When MTB_POSITION[POINTER] matches the WATERMARK field value, actions defined by the AUTOHALT and AUTOSTOP bits are performed.
Page 863 Chapter 43 Micro Trace Buffer (MTB) 43.3.1.4 MTB Base Register (MTB_BASE) The read-only MTB_BASE Register indicates where the RAM is located in the system memory map. This register is provided to enable auto discovery of the MTB RAM location, by a debug agent and is defined by a hardware design parameter. For this device, the base address is defined by the expression: MTB_BASE[BASEADDR] = 0x2000_0000 - (RAM_Size/4) Address: F000_0000h base + Ch offset = F000_000Ch...
Page 864 Memory map and register definition 43.3.1.6 Claim TAG Set Register (MTB_TAGSET) The Claim Tag Set Register returns the number of bits that can be set on a read, and enables individual bits to be set on a write. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Page 865 Chapter 43 Micro Trace Buffer (MTB) 43.3.1.8 Lock Access Register (MTB_LOCKACCESS) The Lock Access Register enables a write access to component registers. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FB0h offset = F000_0FB0h LOCKACCESS Reset MTB_LOCKACCESS field descriptions...
Page 866 Memory map and register definition MTB_AUTHSTAT[3:2] indicates if nonsecure, noninvasive debug is enabled or disabled, while MTB_AUTHSTAT[1:0] indicates the enabled/disabled state of nonsecure, invasive debug. For both 2-bit fields, 0b10 indicates the functionality is disabled and 0b11 indicates it is enabled. Address: F000_0000h base + FB8h offset = F000_0FB8h Reset BIT2...
Page 867 Chapter 43 Micro Trace Buffer (MTB) MTB_DEVICEARCH field descriptions Field Description DEVICEARCH DEVICEARCH Hardwired to 0x4770_0A31. 43.3.1.12 Device Configuration Register (MTB_DEVICECFG) This register indicates the device configuration. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FC8h offset = F000_0FC8h DEVICECFG Reset...
Page 868: Mtb_Dwt Memory Map
Memory map and register definition 43.3.1.14 Peripheral ID Register (MTB_PERIPHIDn) These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FD0h offset + (4d × i), where i=0d to 7d PERIPHID x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset...
Page 869 Chapter 43 Micro Trace Buffer (MTB) MTBDWT memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 43.3.2.1/ F000_1000 MTB DWT Control Register (MTBDWT_CTRL) 2F00_0000h 43.3.2.2/ F000_1020 MTB_DWT Comparator Register (MTBDWT_COMP0) 0000_0000h 43.3.2.3/ F000_1024 MTB_DWT Comparator Mask Register (MTBDWT_MASK0) 0000_0000h MTB_DWT Comparator Function Register 0 43.3.2.4/...
Page 870 Memory map and register definition 43.3.2.1 MTB DWT Control Register (MTBDWT_CTRL) The MTBDWT_CTRL register provides read-only information on the watchpoint configuration for the MTB_DWT. Address: F000_1000h base + 0h offset = F000_1000h NUMCMP DWTCFGCTRL Reset MTBDWT_CTRL field descriptions Field Description 31–28 Number of comparators NUMCMP...
Page 871 Chapter 43 Micro Trace Buffer (MTB) 43.3.2.2 MTB_DWT Comparator Register (MTBDWT_COMPn) The MTBDWT_COMPn registers provide the reference value for comparator n. Address: F000_1000h base + 20h offset + (16d × i), where i=0d to 1d COMP Reset MTBDWT_COMPn field descriptions Field Description COMP...
Page 872 Memory map and register definition MTBDWT_MASKn field descriptions (continued) Field Description If MTBDWT_COMP0 is used as a data value comparator, then MTBDWT_MASK0 should be programmed to zero. 43.3.2.4 MTB_DWT Comparator Function Register 0 (MTBDWT_FCT0) The MTBDWT_FCTn registers control the operation of comparator n. Address: F000_1000h base + 28h offset = F000_1028h Reset DATAVADDR0...
Page 873 Chapter 43 Micro Trace Buffer (MTB) MTBDWT_FCT0 field descriptions (continued) Field Description Comparator match MATCHED If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit. No match.
Page 874 Memory map and register definition 43.3.2.5 MTB_DWT Comparator Function Register 1 (MTBDWT_FCT1) The MTBDWT_FCTn registers control the operation of comparator n. Since the MTB_DWT only supports data value comparisons on comparator 0, there are several fields in the MTBDWT_FCT1 register that are RAZ/WI (bits 12, 11:10, 8). Address: F000_1000h base + 38h offset = F000_1038h Reset FUNCTION...
Page 875 Chapter 43 Micro Trace Buffer (MTB) MTBDWT_FCT1 field descriptions (continued) Field Description No match. Match occurred. 23–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. FUNCTION Function Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a data value and MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION] must be set to zero.
Page 876 Memory map and register definition Reset MTBDWT_TBCTRL field descriptions Field Description 31–28 Number of Comparators NUMCOMP This read-only field specifies the number of comparators in the MTB_DWT. This implementation includes two registers. 27–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Action based on Comparator 1 match ACOMP1 When the MTBDWT_FCT1[MATCHED] is set, it indicates MTBDWT_COMP1 address compare has...
Page 877 Chapter 43 Micro Trace Buffer (MTB) 43.3.2.7 Device Configuration Register (MTBDWT_DEVICECFG) This register indicates the device configuration. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FC8h offset = F000_1FC8h DEVICECFG Reset MTBDWT_DEVICECFG field descriptions...
Page 878: System Rom Memory Map
Memory map and register definition 43.3.2.9 Peripheral ID Register (MTBDWT_PERIPHIDn) These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FD0h offset + (4d × i), where i=0d to 7d PERIPHID x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset...
Page 879 Chapter 43 Micro Trace Buffer (MTB) For core configurations like that supported by Cortex-M0+, ARM recommends that a debugger identifies and connects to the debug components using the CoreSight debug infrastructure. ARM recommends that a debugger follows the flow as shown in the following figure to discover the components in the CoreSight debug infrastructure.
Page 880 Memory map and register definition ROM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 43.3.3.4/ F000_2FD4 Peripheral ID Register (ROM_PERIPHID5) See section 43.3.3.4/ F000_2FD8 Peripheral ID Register (ROM_PERIPHID6) See section 43.3.3.4/ F000_2FDC Peripheral ID Register (ROM_PERIPHID7) See section 43.3.3.4/ F000_2FE0 Peripheral ID Register (ROM_PERIPHID0)
Page 881 Chapter 43 Micro Trace Buffer (MTB) ROM_ENTRYn field descriptions (continued) Field Description Entry 0 (MTB) is hardwired to 0xFFFF_E003; Entry 1 (MTBDWT) to 0xFFFF_F003; Entry 2 (CM0+ ROM Table) to 0xF00F_D003. 43.3.3.2 End of Table Marker Register (ROM_TABLEMARK) This register indicates end of table marker. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Page 882 Memory map and register definition 43.3.3.4 Peripheral ID Register (ROM_PERIPHIDn) These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + FD0h offset + (4d × i), where i=0d to 7d PERIPHID x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset...
Page 883: Flash Memory Controller (Fmc)
Chapter 44 Flash Memory Controller (FMC) 44.1 Introduction The Flash Memory Controller (FMC) is a memory acceleration unit. A list of features provided by the FMC can be found here. • an interface between bus masters and the 32-bit program flash memory. •...
Page 884: Functional Description
Modes of operation • 32-bit prefetch speculation buffer for program flash accesses with controls for instruction/data access • 4-way, 4-set, 32-bit line size program flash memory cache for a total of sixteen 32-bit entries with invalidation control 44.2 Modes of operation The FMC operates only when a bus master accesses the program flash memory.
Page 885 Chapter 44 Flash Memory Controller (FMC) • Data speculation is disabled. • Data caching is enabled. Though the default configuration provides flash acceleration, advanced users may desire to customize the FMC buffer configurations to maximize throughput for their use cases. For example, the user may adjust the controls to enable buffering per access type (data or instruction).
Page 886 Functional description KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 887: Flash Memory Module (Ftfa)
Chapter 45 Flash Memory Module (FTFA) 45.1 Introduction The flash memory module includes the following accessible memory regions: • Program flash memory for vector space and code store Flash memory is ideal for single-supply applications, permitting in-the-field erase and reprogramming operations without the need for any external high voltage power sources. The flash memory module includes a memory controller that executes commands to modify flash memory contents.
Page 888: Block Diagram
Introduction 45.1.1 Features The flash memory module includes the following features. NOTE See the device's Chip Configuration details for the exact amount of flash memory available on your device. 45.1.1.1 Program Flash Memory Features • Sector size of 1 KB •...
Page 889: Glossary
Chapter 45 Flash Memory Module (FTFA) Interrupt Register access Program flash Status registers Memory controller Control registers To MCU's flash controller Program flash Figure 45-1. Flash Block Diagram 45.1.3 Glossary Command write sequence — A series of MCU writes to the flash FCCOB register group that initiates and controls the execution of flash algorithms that are built into the flash memory module.
Page 890: External Signal Description
External Signal Description NVM — Nonvolatile memory. A memory technology that maintains stored data during power-off. The flash array is an NVM using NOR-type flash memory technology. NVM Normal Mode — An NVM mode that provides basic user access to flash memory module resources.
Page 891: Flash Configuration Field Description
Chapter 45 Flash Memory Module (FTFA) Data read from unimplemented memory space in the flash memory module is undefined. Writes to unimplemented or reserved memory space (registers) in the flash memory module are ignored. 45.3.1 Flash Configuration Field Description The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the flash memory module.
Page 892: Register Descriptions
Memory Map and Registers 45.3.2.1 Program Once Field The Program Once Field in the program flash IFR provides 64 bytes of user data storage separate from the program flash main array. The user can program the Program Once Field one time only as there is no program flash IFR erase mechanism available to the user.
Page 893 Chapter 45 Flash Memory Module (FTFA) FTFA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Flash Common Command Object Registers 45.3.3.5/ 4002_0005 (FTFA_FCCOB2) Flash Common Command Object Registers 45.3.3.5/ 4002_0006 (FTFA_FCCOB1) Flash Common Command Object Registers 45.3.3.5/ 4002_0007 (FTFA_FCCOB0)
Page 894 Memory Map and Registers Address: 4002_0000h base + 0h offset = 4002_0000h Read CCIF RDCOLERR ACCERR FPVIOL MGSTAT0 Write Reset FTFA_FSTAT field descriptions Field Description Command Complete Interrupt Flag CCIF Indicates that a flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command, and CCIF stays low until command completion or command violation.
Page 895 Chapter 45 Flash Memory Module (FTFA) FTFA_FSTAT field descriptions (continued) Field Description The value of the MGSTAT0 bit for "command-N" is valid only at the end of the "command-N" execution when CCIF=1 and before the next command has been launched. At some point during the execution of "command-N+1,"...
Page 896 Memory Map and Registers FTFA_FCNFG field descriptions (continued) Field Description 2. verify the erased state, 3. program the security byte in the Flash Configuration Field to the unsecure state, and 4. release MCU security by setting the FSEC[SEC] field to the unsecure state. Erase Suspend ERSSUSP Allows the user to suspend (interrupt) the Erase Flash Sector command while it is executing.
Page 897 Chapter 45 Flash Memory Module (FTFA) FTFA_FSEC field descriptions (continued) Field Description Backdoor key access enabled Backdoor key access disabled 5–4 Mass Erase Enable MEEN Enables and disables mass erase capability of the flash memory module. The state of this field is relevant only when SEC is set to secure outside of NVM Normal Mode.
Page 898 Memory Map and Registers During the reset sequence, the register is loaded from the flash nonvolatile option byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. However, the register is written to 0xFF if the contents of the flash nonvolatile option byte are 0x00.
Page 899 Chapter 45 Flash Memory Module (FTFA) FTFA_FCCOBn field descriptions (continued) Field Description The following table shows a generic flash command format. The first FCCOB register, FCCOB0, always contains the command code. This 8-bit value defines the command to be executed. The command code is followed by the parameters required for this specific flash command, typically an address and/or data values.
Page 900 Memory Map and Registers program flash memory or less, FPROT0 is not used. For configurations with 16 KB of program flash memory or less, FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is not used. The bitfields are defined in each register as follows: Program flash protection register Program flash protection bits...
Page 901: Functional Description
Chapter 45 Flash Memory Module (FTFA) FTFA_FPROTn field descriptions (continued) Field Description In NVM Special mode: All bits of FPROT are writable without restriction. Unprotected areas can be protected and protected areas can be unprotected. Restriction: The user must never write to any FPROT register while a command is running (CCIF=0). Trying to alter data in any protected area in the program flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit.
Page 902: Interrupts
Functional Description Program flash 0x0_0000 FPROT3[PROT0] Program flash size / 32 Program flash size / 32 FPROT3[PROT1] Program flash size / 32 FPROT3[PROT2] Program flash size / 32 FPROT3[PROT3] Program flash size / 32 FPROT0[PROT29] Program flash size / 32 FPROT0[PROT30] Program flash size / 32 FPROT0[PROT31]...
Page 903: Flash Operation In Low-Power Modes
Chapter 45 Flash Memory Module (FTFA) Some devices also generate a bus error response as a result of a Read Collision Error event. See the chip configuration information to determine if a bus error response is also supported. 45.4.3 Flash Operation in Low-Power Modes 45.4.3.1 Wait Mode When the MCU enters wait mode, the flash memory module is not affected.
Page 904: Read While Write (Rww)
Functional Description The MCU must not read from the flash memory while commands are running (as evidenced by CCIF=0) on that block. Read data cannot be guaranteed from a flash block while any command is processing within that block. The block arbitration logic detects any simultaneous access and reports this as a read collision error (see the FSTAT[RDCOLERR] bit).
Page 905 Chapter 45 Flash Memory Module (FTFA) 45.4.8.1 Command Write Sequence Flash commands are specified using a command write sequence illustrated in Figure 45-3. The flash memory module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be zero and the CCIF flag must read 1 to verify that any previous command has completed.
Page 906 Functional Description Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, FSTAT[FPVIOL] (protection error) flag is set. Command processing never proceeds to execution when the parameter or protection step fails.
Page 907 Chapter 45 Flash Memory Module (FTFA) START Read: FSTAT register FCCOB Availability Check CCIF Previous command complete? = ‘1’? Results from previous command Access Error and ACCERR/ Clear the old errors FPVIOL Protection Violation Write 0x30 to FSTAT register Set? Check Write to the FCCOB registers to load the required command parameter.
Page 908 Functional Description FCMD Command Program flash 0 Program flash 1 Function 0x01 Read 1s Section × × Verify that a given number of program flash locations from a starting address are erased. 0x02 Program Check × × Tests previously- programmed locations at margin read levels.
Page 909 Chapter 45 Flash Memory Module (FTFA) FCMD Command Program flash 0 Program flash 1 Function 0x49 Erase All Blocks × × Erase all program flash Unsecure blocks, verify-erase, program security byte to unsecure state, release MCU security. 45.4.8.3 Flash Commands by Mode The following table shows the flash commands that can be executed in each flash operating mode.
Page 910: Margin Read Commands
Functional Description Table 45-3. Allowed Simultaneous Memory Operations Program Flash 0 Program Flash 1 Read Program Sector Erase Read Program Sector Erase Read — Program Program — flash 0 Sector Erase — Read — Program Program — flash 1 Sector Erase —...
Page 911: Flash Command Description
Chapter 45 Flash Memory Module (FTFA) The 'factory' margin is a bigger deviation from the norm, a more stringent read criteria that should only be attempted immediately (or very soon) after completion of an erase or program command, early in the cycling life. 'Factory' margin levels can be used to check that flash memory contents have adequate margin for long-term data retention at the normal level setting.
Page 912 Functional Description 45.4.10.1 Read 1s Block Command The Read 1s Block command checks to see if an entire program flash block has been erased to the specified margin level. The FCCOB flash address bits determine which flash block is erase-verified. Table 45-4.
Page 913 Chapter 45 Flash Memory Module (FTFA) Table 45-7. Read 1s Section Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x01 (RD1SEC) Flash address [23:16] of the first longword to be verified Flash address [15:8] of the first longword to be verified Flash address [7:0] of the first longword to be verified Number of longwords to be verified [15:8]...
Page 914 Functional Description Table 45-10. Program Check Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x02 (PGMCHK) Flash address [23:16] Flash address [15:8] Flash address [7:0] Margin Choice Byte 0 expected data Byte 1 expected data Byte 2 expected data Byte 3 expected data 1.
Page 915 Chapter 45 Flash Memory Module (FTFA) Table 45-12. Program Check Command Error Handling (continued) Error Condition Error Bit Flash address is not longword aligned FSTAT[ACCERR] An invalid margin choice is supplied FSTAT[ACCERR] Either of the margin reads does not match the expected data FSTAT[MGSTAT0] 45.4.10.4 Read Resource Command The Read Resource command allows the user to read data from special-purpose memory...
Page 916 Functional Description After clearing CCIF to launch the Read Resource command, four consecutive bytes are read from the selected resource at the provided relative address and stored in the FCCOB register. The CCIF flag sets after the Read Resource operation completes. The Read Resource command exits with an access error if an invalid resource code is provided or if the address for the applicable area is out-of-range.
Page 917 Chapter 45 Flash Memory Module (FTFA) Upon clearing CCIF to launch the Program Longword command, the flash memory module programs the data bytes into the flash using the supplied address. The targeted flash locations must be currently unprotected (see the description of the FPROT registers) to permit execution of the Program Longword operation.
Page 918 Functional Description within the block is protected (see the description of the FPROT registers). If the erase verify fails, FSTAT[MGSTAT0] is set. The CCIF flag will set after the Erase Flash Block operation has completed. Table 45-19. Erase Flash Block Command Error Handling Error Condition Error Bit Command not available in current mode/security...
Page 919 Chapter 45 Flash Memory Module (FTFA) 45.4.10.7.1 Suspending an Erase Flash Sector Operation To suspend an Erase Flash Sector operation set the FCNFG[ERSSUSP] bit when CCIF, ACCERR, and FPVIOL are clear and the CCOB command field holds the code for the Erase Flash Sector command.
Page 920 Functional Description Note Aborting the erase leaves the bitcells in an indeterminate, partially-erased state. Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. KL27 Sub-Family Reference Manual , Rev.
Page 921 Chapter 45 Flash Memory Module (FTFA) Enter with CCIF = 1 Command Initiation ERSSCR Command (Write FCCOB) Memory Controller Command Processing Launch/Resume Command (Clear CCIF) Resume ERSSCR SUSPACK=1 Next Command CCIF = 1? (Write FCCOB) Restore Erase Algo Start Clear SUSPACK = 0 Interrupt? Execute DONE?
Page 922 Functional Description 45.4.10.8 Read 1s All Blocks Command The Read 1s All Blocks command checks if the program flash blocks have been erased to the specified read margin level, if applicable, and releases security if the readout passes, i.e. all data reads as '1'. Table 45-22.
Page 923 Chapter 45 Flash Memory Module (FTFA) 45.4.10.9 Read Once Command The Read Once command provides read access to special 64-byte fields located in the program flash 0 IFR (see Program Flash IFR Map Program Once Field). Access to the Program Once field is via 16 records (index values 0x00 - 0x0F), each 4 bytes long. These fields are programmed using the Program Once command described in Program Once...
Page 924 Functional Description Table 45-27. Program Once Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x43 (PGMONCE) Program Once record index (0x00 - 0x0F) Not Used Not Used Program Once byte 0 value Program Once byte 1 value Program Once byte 2 value Program Once byte 3 value After clearing CCIF to launch the Program Once command, the flash memory module first verifies that the selected record is erased.
Page 925 Chapter 45 Flash Memory Module (FTFA) After clearing CCIF to launch the Erase All Blocks command, the flash memory module erases all program flash memory, then verifies that all are erased. If the flash memory module verifies that all flash memories were properly erased, security is released by setting the FSEC[SEC] field to the unsecure state.
Page 926 Functional Description Configuration Field (see Flash Configuration Field Description). The column labelled Flash Configuration Field offset address shows the location of the matching byte in the Flash Configuration Field. Table 45-31. Verify Backdoor Access Key Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] Flash Configuration Field Offset Address 0x45 (VFYKEY)
Page 927: Security
Chapter 45 Flash Memory Module (FTFA) 45.4.10.13 Erase All Blocks Unsecure Command The Erase All Blocks Unsecure operation erases all flash memory, verifies all memory contents, programs the security byte in the Flash Configuration Field to the unsecure state, and releases MCU security. Table 45-33.
Page 928 Functional Description Table 45-35. FSEC register fields FSEC field Description KEYEN Backdoor Key Access MEEN Mass Erase Capability FSLACC Freescale Factory Access MCU security 45.4.11.1 Flash Memory Access by Mode and Security The following table summarizes how access to the flash memory module is affected by security and operating mode.
Page 929: Reset Sequence
Chapter 45 Flash Memory Module (FTFA) 0000_0000_0000_0000h and FFFF_FFFF_FFFF_FFFFh are not accepted by the Verify Backdoor Access Key command as valid comparison values. While the Verify Backdoor Access Key command is active, program flash memory is not available for read access and returns invalid data.
Page 930 Functional Description FSTAT[CCIF] is cleared throughout the reset sequence. The flash memory module holds off CPU access during the reset sequence. Flash reads are possible when the hold is removed. Completion of the reset sequence is marked by setting CCIF which enables flash user commands.
Page 931 Appendix A Release Notes for Revision 5 A.1 General changes throughout • Corrected Flash memory information in Chapter - 4. • Updated status of COP Watchdog from static to functional under Stop and VLPS modes in Table 7-2. Module operation in low power modes. Also added 12-bit DAC description. •...
Page 932 Memory Map chapter changes A.5 Memory Map chapter changes No substantial content changes A.6 Clock Distribution chapter changes No substantial content changes A.7 Reset and Boot chapter changes No substantial content changes A.8 Power Management chapter changes No substantial content changes A.9 Security chapter changes No substantial content changes A.10 Debug chapter changes...
Page 933 Appendix A Release Notes for Revision 5 A.12 PORT changes • No substantial content changes A.13 SIM changes • Added "ADC trigger selection" and "COP configuration" to the features list A.14 Kinetis ROM Bootloader changes • Added "FlashEraseRegion Command Packet Format (Example)" table to the topic: FlashEraseRegion command •...
Page 934 Crossbar switch module changes A.18 Crossbar switch module changes • Features • Replaced "64-bit data bus" with "Up to single-clock 32-bit transfer". • Removed bullet beginning with, "Operation at a 1-to-1 clock frequency..." from Features. • General operation : Removed paragraph beginning with "A master is given control of the targeted slave..." and the following list, beginning with "A higher priority master has...".
Page 935 Appendix A Release Notes for Revision 5 A.24 ADC changes • No substantial content changes A.25 CMP changes • No substantial content changes A.26 DAC changes • No substantial content changes A.27 VREF changes • Added Internal Voltage Regulator topic to the chapter. A.28 MCG_Lite changes •...
Page 936 PIT module changes A.31 PIT module changes • No substantial content changes A.32 LPTMR changes Updated CNR[COUNTER] field description. A.33 RTC changes • No substantial content changes A.34 USB full speed changes Added new topic under "Functional description": "On-chip transceiver required external components." Removed OTG Control (OTGCTL) register In the section, "On-chip transceiver required external components": •...
Page 937 Appendix A Release Notes for Revision 5 A.37 I2C changes • “IIAAS” corrected to “IAAS”, in the figure "Typical I2C interrupt routine" under the section "Initialization/application information". A.38 LPUART changes • No substantial content changes A.39 UART changes • No substantial content changes A.40 FlexIO changes •...
Page 938 MTB configuration changes A.44 MTB configuration changes • No substantial content changes A.45 FMC changes • No substantial content changes A.46 FTFA changes • No substantial content changes KL27 Sub-Family Reference Manual , Rev. 5, 01/2016 Freescale Semiconductor, Inc.
Page 939 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express Home Page: or implied copyright licenses granted hereunder to design or fabricate freescale.com any integrated circuits based on the information in this document. Web Support: Freescale reserves the right to make changes without further notice to any products herein.

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NXP Semiconductors MKL27Z128VFM4 Reference Manual

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3

Core Overview

Chapter 4 Memory Map

Chapter 5

Chapter 6 Reset and Boot

Chapter 7 Power Management

Chapter 8 Security

Chapter 9 Debug

Chapter 10 Pinouts and Packaging

Chapter 11 Port Control and Interrupts (PORT)

Chapter 12 System Integration Module (SIM)

Chapter 13

Chapter 14 System Mode Controller (SMC)

Chapter 15 Power Management Controller (PMC)

Chapter 16 Miscellaneous Control Module (MCM)

Chapter 17 Crossbar Switch Lite (AXBS-Lite)

Chapter 18 Low-Leakage Wakeup Unit (LLWU)

Chapter 19 Peripheral Bridge (AIPS-Lite)

Chapter 20 Direct Memory Access Multiplexer (DMAMUX)

Chapter 21 DMA Controller Module

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Summary of Contents for NXP Semiconductors MKL27Z128VFM4