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• SARn is loaded with the source (read) address. If the transfer is from a
peripheral device to memory or to another peripheral, the source address is the
location of the peripheral data register. If the transfer is from memory to a
peripheral device or to memory, the source address is the starting address of the
data block. This can be any appropriately aligned address.
• DARn is initialized with the destination (write) address. If the transfer is from a
peripheral device to memory, or from memory to memory, DARn is loaded with
the starting address of the data block to be written. If the transfer is from
memory to a peripheral device, or from a peripheral device to a peripheral
device, DARn is loaded with the address of the peripheral data register. This
address can be any appropriately aligned address.
• SARn and DARn change after each data transfer depending on DCRn[SSIZE,
DSIZE, SINC, DINC, SMOD, DMOD] and the starting addresses. Increment
values can be 1, 2, or 4 for 8-bit, 16-bit, or 32-bit transfers, respectively. If the
address register is programmed to remain unchanged, the register is not
incremented after the data transfer.
• BCRn[BCR] must be loaded with the total number of bytes to be transferred. It
is decremented by 1, 2, or 4 at the end of each transfer, depending on the transfer
size. DSRn[DONE] must be cleared for channel startup.
• After the channel has been initialized, it may be started by setting DCRn[START] or
a properly selected peripheral DMA request, depending on the status of
DCRn[ERQ]. For a software-initiated transfer, the channel can be started by setting
DCRn[START] as part of a single 32-bit write to the last 32 bits of the TCDn; that is,
it is not required to write the DCRn with START cleared and then perform a second
write to explicitly set START.
• Programming the channel for a software-initiated request causes the channel to
request the system bus and start transferring data immediately. If the channel is
programmed for peripheral-initiated request, a properly selected peripheral DMA
request must be asserted before the channel begins the system bus transfers.
• The hardware can automatically clear DCRn[ERQ], disabling the peripheral request,
when BCRn reaches zero by setting DCRn[D_REQ].
• Changes to DCRn are effective immediately while the channel is active. To avoid
problems with changing a DMA channel setup, write a one to DSRn[DONE] to stop
the DMA channel.
Freescale Semiconductor, Inc.
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 21 DMA Controller Module
321
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