Uart Match Address Registers 2 (Uartx_Ma2); Uart Control Register 4 (Uartx_C4) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map and registers

38.4.10 UART Match Address Registers 2 (UARTx_MA2)

These registers can be read and written at anytime. The MA1 and MA2 registers are
compared to input data addresses when the most significant bit is set and the associated
C4[MAEN] field is set. If a match occurs, the following data is transferred to the data
register. If a match fails, the following data is discarded.
Address: 4006_C000h base + 9h offset = 4006_C009h
Bit 7
Read
Write
Reset 0
Field
MA Match Address

38.4.11 UART Control Register 4 (UARTx_C4)

Address: 4006_C000h base + Ah offset = 4006_C00Ah
Bit 7
Read
MAEN1
Write
Reset 0
Field
7 Match Address Mode Enable 1
MAEN1
See Match address operation
0 All data received is transferred to the data buffer if MAEN2 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA1 register. If no match occurs, the data is
discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when
C7816[ISO7816E] is set/enabled.
6 Match Address Mode Enable 2
MAEN2
See Match address operation
0 All data received is transferred to the data buffer if MAEN1 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA2 register. If no match occurs, the data is
discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when
C7816[ISO7816E] is set/enabled.
694
6 5
0 0
UARTx_MA2 field descriptions
6 5
MAEN2 M10
0 0
UARTx_C4 field descriptions
for more information.
for more information.
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
4 3
MA
0 0
Description
4 3
BRFA
0 0
Description
2 1
0 0
2 1
0 0
Freescale Semiconductor, Inc.
0
0
0
0