Register Definition - NXP Semiconductors MKL27Z128VFM4 Reference Manual

SBR12:0
ASYNCH
BAUDRATE
MODULE
CLOCK
GENERATOR
RE
CONTROL
RAF
RxD
LOOPS
RECEIVER
RSRC SOURCE
CONTROL
From Transmitter
RxD
ACTIVE EDGE

37.3 Register definition

The LPUART includes registers to control baud rate, select LPUART options, report
LPUART status, and for transmit/receive data. Access to an address outside the valid
memory map will generate a bus error.
Absolute
address
(hex)
4005_4000 LPUART Baud Rate Register (LPUART0_BAUD)
4005_4004 LPUART Status Register (LPUART0_STAT)
4005_4008 LPUART Control Register (LPUART0_CTRL)
4005_400C LPUART Data Register (LPUART0_DATA)
4005_4010 LPUART Match Address Register (LPUART0_MATCH)
4005_5000 LPUART Baud Rate Register (LPUART1_BAUD)
4005_5004 LPUART Status Register (LPUART1_STAT)
4005_5008 LPUART Control Register (LPUART1_CTRL)
4005_500C LPUART Data Register (LPUART1_DATA)
4005_5010 LPUART Match Address Register (LPUART1_MATCH)
Freescale Semiconductor, Inc.
Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART)
RECEIVE
DETECT
Figure 37-2. LPUART receiver block diagram
LPUART memory map
Register name
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
INTERNAL BUS
DATA BUFFER
VARIABLE 12-BIT RECEIVE
SHIFT REGISTER
SHIFT DIRECTION
PE
PARITY
LOGIC
PT
Width
Access
(in bits)
32
32
32
32
32
32
32
32
32
32
M
M10
LBKDE
MSBF
RXINV
WAKEUP
LOGIC
DMA Requests
IRQ / DMA
LOGIC
IRQ Requests
Section/
Reset value
page
R/W 0F00_0004h 37.3.1/652
R/W 00C0_0000h 37.3.2/654
R/W 0000_0000h 37.3.3/658
R/W 0000_1000h 37.3.4/663
R/W 0000_0000h 37.3.5/665
R/W 0F00_0004h 37.3.1/652
R/W 00C0_0000h 37.3.2/654
R/W 0000_0000h 37.3.3/658
R/W 0000_1000h 37.3.4/663
R/W 0000_0000h 37.3.5/665
651