Sai Transmit Data Register (I2Sx_Tdrn); Sai Transmit Mask Register (I2Sx_Tmr) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Memory map and register definition

First Bit Shifted

Configures the bit index for the first bit transmitted for each word in the frame. If configured for MSB First,

the index of the next bit transmitted is one less than the current bit transmitted. If configured for LSB First,

the index of the next bit transmitted is one more than the current bit transmitted. The value written must be

greater than or equal to the word width when configured for MSB First. The value written must be less

than or equal to 31-word width when configured for LSB First.

This field is reserved.

This read-only field is reserved and always has the value 0.

40.4.6 SAI Transmit Data Register (I2Sx_TDRn)

Address: 4002_F000h base + 20h offset + (4d × i), where i=0d to 0d

Transmit Data Register

The corresponding TCR3[TCE] bit must be set before accessing the channel's transmit data register.

Writes to this register when the transmit FIFO is not full will push the data written into the transmit data

FIFO. Writes to this register when the transmit FIFO is full are ignored.

This register is double-buffered and updates:

1. When TCSR[TE] is first set

2. At the end of each frame.

This allows the masked words in each frame to change from frame to frame.

Address: 4002_F000h base + 60h offset = 4002_F060h

I2Sx_TCR5 field descriptions (continued)

I2Sx_TDRn field descriptions

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Freescale Semiconductor, Inc.