Port Data Output Register (Gpiox_Pdor) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Absolute
address
(hex)
400F_F0C4 Port Set Output Register (GPIOD_PSOR)
400F_F0C8 Port Clear Output Register (GPIOD_PCOR)
400F_F0CC Port Toggle Output Register (GPIOD_PTOR)
400F_F0D0 Port Data Input Register (GPIOD_PDIR)
400F_F0D4 Port Data Direction Register (GPIOD_PDDR)
400F_F100 Port Data Output Register (GPIOE_PDOR)
400F_F104 Port Set Output Register (GPIOE_PSOR)
400F_F108 Port Clear Output Register (GPIOE_PCOR)
400F_F10C Port Toggle Output Register (GPIOE_PTOR)
400F_F110 Port Data Input Register (GPIOE_PDIR)
400F_F114 Port Data Direction Register (GPIOE_PDDR)

41.3.1 Port Data Output Register (GPIOx_PDOR)

This register configures the logic levels that are driven on each general-purpose output
pins.
Do not modify pin configuration registers associated with pins
not available in your selected package. All unbonded pins not
available in your package will default to DISABLE state for
lowest power consumption.
Address: Base address + 0h offset
Bit 31 30 29 28 27 26
R
W
0 0 0 0 0 0
Reset
Freescale Semiconductor, Inc.
GPIO memory map (continued)
Register name
25 24 23 22 21 20 19 18
0 0 0 0 0 0 0 0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 41 General-Purpose Input/Output (GPIO)
Width
(in bits)
32
32
32
32
32
32
32
32
32
32
32
NOTE
17 16 15 14 13 12 11 10
PDO
0 0 0 0 0 0 0 0
Section/
Access Reset value
W
(always 0000_0000h 41.3.2/826
reads 0)
W
(always 0000_0000h 41.3.3/826
reads 0)
W
(always 0000_0000h 41.3.4/827
reads 0)
R 0000_0000h 41.3.5/827
R/W 0000_0000h 41.3.6/828
R/W 0000_0000h 41.3.1/825
W
(always 0000_0000h 41.3.2/826
reads 0)
W
(always 0000_0000h 41.3.3/826
reads 0)
W
(always 0000_0000h 41.3.4/827
reads 0)
R 0000_0000h 41.3.5/827
R/W 0000_0000h 41.3.6/828
9 8 7 6 5 4 3
0 0 0 0 0 0 0
page
2 1 0
0 0 0
825