Dac Data Low Register (Dacx_Datnl); Dac Data High Register (Dacx_Datnh) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Absolute
address
(hex)
4003_F000 DAC Data Low Register (DAC0_DAT0L)
4003_F001 DAC Data High Register (DAC0_DAT0H)
4003_F002 DAC Data Low Register (DAC0_DAT1L)
4003_F003 DAC Data High Register (DAC0_DAT1H)
4003_F020 DAC Status Register (DAC0_SR)
4003_F021 DAC Control Register (DAC0_C0)
4003_F022 DAC Control Register 1 (DAC0_C1)
4003_F023 DAC Control Register 2 (DAC0_C2)

25.4.1 DAC Data Low Register (DACx_DATnL)

Address: 4003_F000h base + 0h offset + (2d × i), where i=0d to 1d
Bit 7
Read
Write
Reset
0
Field
DATA0 DATA0
When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following
formula: V
When the DAC buffer is enabled, DATA is mapped to the 16-word buffer.

25.4.2 DAC Data High Register (DACx_DATnH)

Address: 4003_F000h base + 1h offset + (2d × i), where i=0d to 1d
Bit 7
Read
Write
Reset
0
Field
7–4 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
DATA1 DATA1
Freescale Semiconductor, Inc.
DAC memory map
Register name
6 5
0 0
DACx_DATnL field descriptions
= V * (1 + DACDAT0[11:0])/4096
out in
6 5
0
0 0
DACx_DATnH field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 25 12-bit Digital-to-Analog Converter (DAC)
Width
Access
(in bits)
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
4 3
DATA0
0 0
Description
4 3
0 0
Description
Section/
Reset value
page
00h 25.4.1/415
00h 25.4.2/415
00h 25.4.1/415
00h 25.4.2/415
See section 25.4.3/416
00h 25.4.4/417
00h 25.4.5/418
01h 25.4.6/418
2 1
0 0
2 1
DATA1
0 0
0
0
0
0
415