Lpuart Match Address Register (Lpuartx_Match); Functional Description; Baud Rate Generation - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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37.3.5 LPUART Match Address Register (LPUARTx_MATCH)

Address: Base address + 10h offset

This field is reserved.

This read-only field is reserved and always has the value 0.

Match Address 2

The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and

the associated BAUD[MAEN] bit is set. If a match occurs, the following data is transferred to the data

associated BAUD[MAEN] bit is clear.

This field is reserved.

This read-only field is reserved and always has the value 0.

Match Address 1

The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and

the associated BAUD[MAEN] bit is set. If a match occurs, the following data is transferred to the data

associated BAUD[MAEN] bit is clear.

The LPUART supports full-duplex, asynchronous, NRZ serial communication and

comprises a baud rate generator, transmitter, and receiver block. The transmitter and

receiver operate independently, although they use the same baud rate generator. The

following describes each of the blocks of the LPUART.

A 13-bit modulus counter in the baud rate generator derive the baud rate for both the

receiver and the transmitter. The value from 1 to 8191 written to SBR[12:0] determines

the baud clock divisor for the asynchronous LPUART baud clock. The SBR bits are in

the LPUART baud rate registers, BDH and BDL. The baud rate clock drives the receiver,

Freescale Semiconductor, Inc.

Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART)

LPUARTx_MATCH field descriptions

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016