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Functional description
To enter LIRC2M mode from HIRC or EXT mode:
1. Write 0b to MCG_C2[IRCS] to select LIRC 2M.
2. Write 1b to MCG_C1[IRCLKEN] to enable LIRC clock (optional).
3. Write 01b to MCG_C1[CLKS] to select LIRC clock source.
4. Check MCG_S[CLKST] to confirm LIRC clock source is selected.
To enter LIRC8M mode from HIRC or EXT mode:
1. Write 1b to MCG_C2[IRCS] to select LIRC 8M.
2. Write 1b to MCG_C1[IRCLKEN] to enable LIRC clock (optional).
3. Write 01b to MCG_C1[CLKS] to select LIRC clock source.
4. Check MCG_S[CLKST] to confirm LIRC clock source is selected.
27.3.2 LIRC divider 1
In the MCG_Lite module, there is a divider for LIRC clock. The divider
supports /1, /2, /4, /8, /16, /32, /64, and /128 division factors. For details, see the register
field description of MCG_SC[FCRDIV]. The divided clock of LIRC DIV1 is one of the
inputs of clock select switch. It is the input for the 2nd LIRC DIV as well. See the Chip
Configuration information for more details.
27.3.3 LIRC divider 2
In the MCG_Lite module, there is another divider to further divide the LIRC clock,
named LIRC DIV2. This divider supports /1, /2, /4, /8, /16, /32, /64, and /128 division
factors. For details, see the register field description of MCG_MC[LIRC_DIV2]. The
divided clock of LIRC DIV2 is MCGIRCLK, and it can be used as peripheral clock. See
the Chip Configuration information for more details.
27.3.4 Enable LIRC in Stop mode
In Stop mode, HIRC is disabled to save power. For LIRC, by default it is disabled as
well. To enable LIRC in Stop mode, write 1b to MCG_C1[IREFSTEN] and
MCG_C1[IRCLKEN] before entering Stop mode.
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KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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