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11.7.4 Interrupt Status Flag Register (PORTx_ISFR)
The corresponding bit is read only for pins that do not support interrupt generation.
The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt
Status Flag for each pin is also visible in the corresponding Pin Control Register, and
each flag can be cleared in either location.
Address: Base address + A0h offset
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
ISF
Interrupt Status Flag
Each bit in the field indicates the detection of the configured interrupt of the same number as the field.
0
Configured interrupt is not detected.
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level
sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is
cleared.
11.8 Functional description
11.8.1 Pin control
Each port pin has a corresponding Pin Control register, PORT_PCRn, associated with it.
The upper half of the Pin Control register configures the pin's capability to either
interrupt the CPU or request a DMA transfer, on a rising/falling edge or both edges as
well as a logic level occurring on the port pin. It also includes a flag to indicate that an
interrupt has occurred.
The lower half of the Pin Control register configures the following functions for each pin
within the 32-bit port.
• Pullup or pulldown enable on selected pins
• Drive strength and slew rate configuration on selected pins
Freescale Semiconductor, Inc.
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
PORTx_ISFR field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 11 Port Control and Interrupts (PORT)
17
16
15
14
13
12
11
10
ISF
w1c
0
0
0
0
0
0
0
0
Description
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
1
0
0
0
139
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