Table of Contents
Advertisement
RNFULLF is set when more than three 16-bit words or six 8-bit bytes of data remain in
the receive FIFO provided C3[4] = 0 or when more than two 16-bit words or four 8-bit
bytes of data remain in the receive FIFO provided C3[4] = 1.
Clearing this interrupt depends on the state of C3[3] and the status of RNFULLF. Refer
to the description of the SPI status (S) register.
35.5.13.7 Asynchronous interrupt in low-power modes
When the CPU is in Wait mode or Stop mode and the SPI module receives a
transmission, the SPI module can generate an asynchronous interrupt to wake the CPU
from the low power mode. The module generates the asynchronous interrupt only when
all of the following conditions apply:
1. C1[SPIE] is set to 1.
2. The CPU is in Wait mode—in which case C2[SPISWAI] must be 1—or in Stop
mode where the peripheral bus clock is stopped but internal logic states are retained.
3. The SPI module is in slave mode.
4. The received transmission ends.
5. When the FIFO feature is supported, FIFO mode is disabled: C3[FIFOMODE] is 0.
After the interrupt wakes the CPU and the peripheral bus clock is active again, the SPI
module copies the received data from the shifter into the Data register and generates flags
or DMA request signals. During the wakeup phase, a continuous transmission from a
master would destroy the first received data.
35.6 Initialization/application information
This section discusses an example of how to initialize and use the SPI.
When operating the SPI at the maximum baud rate it must be
configured for 16 bit operation.
35.6.1 Initialization sequence
Before the SPI module can be used for communication, an initialization procedure must
be carried out, as follows:
Freescale Semiconductor, Inc.
NOTE
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 35 Serial Peripheral Interface (SPI)
605
Advertisement
Table of Contents
