External Signals - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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External signals

In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter

is disabled after completing the current transmit frame, and, if the Receiver Stop Enable

(RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive

frame. Entry into Stop mode is prevented–not acknowledged–while waiting for the

transmitter and receiver to be disabled at the end of the current frame.

40.2.3.3 Low-leakage modes

When entering low-leakage modes, the Stop Enable (TCSR[STOPE] and

RCSR[STOPE]) bits are ignored and the SAI is disabled after completing the current

transmit and receive Frames. Entry into stop mode is prevented (not acknowledged)

while waiting for the transmitter and receiver to be disabled at the end of the current

40.2.3.4 Debug mode

In Debug mode, the SAI transmitter and/or receiver can continue operating provided the

Debug Enable bit is set. When TCSR[DBGE] or RCSR[DBGE] bit is clear and Debug

mode is entered, the SAI is disabled after completing the current transmit or receive

frame. The transmitter and receiver bit clocks are not affected by Debug mode.

40.3 External signals

Transmit Bit Clock. The bit clock is an input when

externally generated and an output when

internally generated.

Transmit Frame Sync. The frame sync is an input

sampled synchronously by the bit clock when

externally generated and an output generated

synchronously by the bit clock when internally

Transmit Data. The transmit data is generated

synchronously by the bit clock and is tristated

whenever not transmitting a word.

Receive Bit Clock. The bit clock is an input when

externally generated and an output when

internally generated.

Receive Frame Sync. The frame sync is an input

sampled synchronously by the bit clock when

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KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Freescale Semiconductor, Inc.