I2S/Sai Clocking - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Module clocks
2
5.7.10 I S/SAI clocking
The audio master clock (MCLK) is used to generate the bit clock when the receiver or
transmitter is configured for an internally generated bit clock. The audio master clock can
also be output to or input from a pin. The transmitter and receiver have the same audio
master clock inputs.
Each SAI peripheral can control the input clock selection, pin direction and divide ratio
of one audio master clock.
2
The I S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can
be generated internally from the audio master clock or supplied externally. The module
also supports the option for synchronous operation between the receiver and transmitter.
The transmitter and receiver can independently select between the bus clock and the
audio master clock to generate the bit clock.
The MCLK and BCLK source options appear in the following figure.
78
Clock Generation
MCGPCLK
11
MCGIRCLK
10
1
OSCERCLK
01
System Clock
00
0
MCLK_IN
2
Figure 5-10. I S/SAI clock generation
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
I2S/SAI
I2Sx_TCR2/RCR2
MCLK
Bus Clock
[MSEL]
I2Sx_MCR[MOE]
I2Sx_MCR[MICS]
MCLK_OUT Direction
Control
Pad Interface Logic
BCLK_OUT
11 Bit
10
Clock
1
01
Divider
00
BCLK_IN
0
[DIV] [BCD]
Freescale Semiconductor, Inc.
BCLK