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NXP Semiconductors MKL27Z256VLH4 Reference Manual (939 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 4 MB

Table of Contents
3
Chapter 1 About this Document

37
- Overview
  37
  - Purpose
    37
  - Audience
    37
- Conventions
  37
  - Numbering Systems
    37
  - Typographic Notation
    38
  - Special Terms
    38
Chapter 2 Introduction

39
- Overview
  39
  - Sub-Family Introduction
    39
- Module Functional Categories
  40
  - ARM Cortex-M0+ Core Modules
    41
  - System Modules
    41
  - Memories and Memory Interfaces
    42
  - Clocks
    42
  - Security and Integrity Modules
    43
  - Analog Modules
    43
  - Timer Modules
    43
  - Communication Interfaces
    44
  - Human-Machine Interfaces
    45
- Module to Module Interconnects
  45
  - Interconnection Overview
    45
  - Analog Reference Options
    47
Chapter 3

49
Core Overview

49
- ARM Cortex-M0+ Core Introduction
  49
  - Buses, Interconnects, and Interfaces
    49
  - System Tick Timer
    49
  - Debug Facilities
    49
  - Core Privilege Levels
    50
- Nested Vectored Interrupt Controller (NVIC)
  50
- AWIC Introduction
  53
  - Wake-Up Sources
    53
Chapter 4 Memory Map

55
- Introduction
  55
- Flash Memory
  55
  - Flash Memory Map
    55
  - Flash Security
    56
  - Flash Modes
    56
  - Erase All Flash Contents
    56
  - FTFA_FOPT Register
    57
- Sram
  57
  - SRAM Sizes
    57
  - SRAM Ranges
    57
  - SRAM Retention in Low Power Modes
    58
- System Register File
  58
- System Memory Map
  59
- Bit Manipulation Engine
  60
- Peripheral Bridge (AIPS-Lite) Memory Map
  60
  - Read-After-Write Sequence and Required Serialization of Memory Operations
    61
  - Peripheral Bridge (AIPS-Lite) Memory Map
    61
Chapter 5

65
- Introduction
  65
- Programming Model
  65
- High-Level Device Clocking Diagram
  65
- Clock Definitions
  66
  - Device Clock Summary
    67
- Internal Clocking Requirements
  69
  - Clock Divider Values after Reset
    70
  - VLPR Mode Clocking
    70
- Clock Gating
  71
- Module Clocks
  71
  - PMC 1-Khz LPO Clock
    72
  - COP Clocking
    72
  - RTC Clocking
    73
  - RTC_CLKOUT and CLKOUT32K Clocking
    73
  - LPTMR Clocking
    74
  - TPM Clocking
    75
  - USB FS Device Only Controller Clocking
    75
  - LPUART Clocking
    76
  - Flexio Clocking
    77
  - I2S/SAI Clocking
    78
Chapter 6 Reset and Boot

79
- Introduction
  79
- Reset
  79
  - Power-On Reset (POR)
    80
  - System Reset Sources
    80
  - MCU Resets
    83
  - RESET Pin
    84
- Boot
  84
  - Boot Sources
    85
  - FOPT Boot Options
    85
  - Boot Sequence
    87
Chapter 7 Power Management

89
- Introduction
  89
- Clocking Modes
  89
  - Partial Stop
    89
  - DMA Wakeup
    90
  - Compute Operation
    91
  - Peripheral Doze
    92
  - Clock Gating
    93
- Power Modes
  93
- Entering and Exiting Power Modes
  95
- Module Operation in Low-Power Modes
  96
Chapter 8 Security

101
- Introduction
  101
  - Flash Security
    101
  - Security Interactions with Other Modules
    101
Chapter 9 Debug

103
- Introduction
  103
- Debug Port Pin Descriptions
  103
- SWD Status and Control Registers
  104
  - MDM-AP Control Register
    105
  - MDM-AP Status Register
    106
- Debug Resets
  108
- Micro Trace Buffer (MTB)
  108
- Debug in Low-Power Modes
  109
- Debug and Security
  110
Chapter 10 Pinouts and Packaging

111
- Introduction
  111
- Signal Multiplexing Integration
  111
  - Clock Gating
    112
  - Signal Multiplexing Constraints
    112
- KL27 Signal Multiplexing and Pin Assignments
  112
- KL27 Family Pinouts
  115
- Module Signal Description Tables
  118
  - Core Modules
    118
  - System Modules
    119
  - Clock Modules
    119
  - Analog
    119
  - Timer Modules
    120
  - Communication Interfaces
    121
  - Human-Machine Interfaces (HMI)
    124
Chapter 11 Port Control and Interrupts (PORT)

125
- Chip-Specific PORT Information
  125
- Port Control and Interrupt Summary
  126
- Introduction
  127
- Overview
  127
  - Features
    127
  - Modes of Operation
    128
- External Signal Description
  129
- Detailed Signal Description
  129
- Memory Map and Register Definition
  129
- Functional Description
  139
  - Pin Control
    139
  - Global Pin Control
    140
  - External Interrupts
    140
Chapter 12 System Integration Module (SIM)

143
Chapter 13

175
- Memory Maps
  175
- The Kinetis Bootloader Configuration Area (BCA)
  176
- Start-Up Process
  177
- Clock Configuration
  180
- Bootloader Entry Point
  180
- Bootloader Protocol
  181
- Bootloader Packet Types
  186
- Bootloader Command API
  193
- Bootloader Exit State
  208
- Peripherals Supported
  209
  - I2C Peripheral
    209
  - SPI Peripheral
    211
  - USB Peripheral
    213
- Get/Setproperty Command Properties
  217
  - Property Definitions
    219
- Kinetis Bootloader Status Error Codes
  220
- Bootloader Errata
  221
Chapter 14 System Mode Controller (SMC)

223
- Chip-Specific SMC Information
  223
- Introduction
  223
- Modes of Operation
  223
- Memory Map and Register Descriptions
  225
- Functional Description
  230
  - Power Mode Transitions
    230
  - Power Mode Entry/Exit Sequencing
    233
  - Run Modes
    234
  - Wait Modes
    236
  - Stop Modes
    237
  - Debug in Low Power Modes
    240
Chapter 15 Power Management Controller (PMC)

241
- Introduction
  241
- Features
  241
- Low-Voltage Detect (LVD) System
  241
  - LVD Reset Operation
    242
  - LVD Interrupt Operation
    242
  - Low-Voltage Warning (LVW) Interrupt Operation
    242
- I/O Retention
  243
- Memory Map and Register Descriptions
  243
Chapter 16 Miscellaneous Control Module (MCM)

249
- Introduction
  249
  - Features
    249
- Memory Map/Register Descriptions
  249
Chapter 17 Crossbar Switch Lite (AXBS-Lite)

257
- Chip-Specific AXBS-Lite Information
  257
  - Crossbar-Light Switch Master Assignments
    257
  - Crossbar Switch Slave Assignments
    257
- Introduction
  257
  - Features
    258
- Memory Map / Register Definition
  258
- Functional Description
  258
  - General Operation
    258
  - Arbitration
    259
- Initialization/Application Information
  261
- LLWU Interrupt
  263
  - Wake-Up Sources
    263
- Introduction
  264
  - Features
    264
Chapter 18 Low-Leakage Wakeup Unit (LLWU)

265
- Modes of Operation
  265
- Block Diagram
  266
- LLWU Signal Descriptions
  267
- Memory Map/Register Definition
  267
- Functional Description
  281
  - LLS Mode
    282
  - VLLS Modes
    282
  - Initialization
    282
Chapter 19 Peripheral Bridge (AIPS-Lite)

283
- Chip-Specific AIPS-Lite Information
  283
  - Number of Peripheral Bridges
    283
  - Memory Maps
    283
- Introduction
  283
  - Features
    283
  - General Operation
    284
- Memory Map/Register Definition
  284
- Functional Description
  291
  - Access Support
    291
- Chip-Specific DMAMUX Information
  293
  - DMA MUX Request Sources
    293
Chapter 20 Direct Memory Access Multiplexer (DMAMUX)

295
- DMA Transfers Via PIT Trigger
  295
- Introduction
  295
  - Overview
    295
  - Features
    296
  - Modes of Operation
    296
- External Signal Description
  297
- Memory Map/Register Definition
  297
  - Channel Configuration Register (Dmamuxx_Chcfgn)
    297
- Functional Description
  298
- Initialization/Application Information
  303
  - Reset
    303
  - Enabling and Configuring Sources
    303
Chapter 21 DMA Controller Module

307
- Introduction
  307
  - Overview
    307
  - Features
    308
- DMA Transfer Overview
  309
- Memory Map/Register Definition
  310
- Functional Description
  319
Chapter 22 Reset Control Module (RCM)

325
- Introduction
  325
- Reset Memory Map and Register Descriptions
  325
Chapter 23 Analog-To-Digital Converter (ADC)

335
Chapter 24 Comparator (CMP)

391
- Chip-Specific CMP Information
  391
  - CMP Instantiation Information
    391
  - CMP Input Connections
    391
  - CMP External References
    392
  - CMP Trigger Mode
    392
- Introduction
  393
  - CMP Features
    393
  - 6-Bit DAC Key Features
    394
  - ANMUX Key Features
    394
  - CMP, DAC and ANMUX Diagram
    394
  - CMP Block Diagram
    395
- Memory Map/Register Definitions
  397
- Functional Description
  402
  - CMP Functional Modes
    403
  - Power Modes
    406
  - Startup and Operation
    407
  - Low-Pass Filter
    408
- CMP Interrupts
  410
- DMA Support
  410
- CMP Asynchronous DMA Support
  410
- Digital-To-Analog Converter
  411
- DAC Functional Description
  411
  - Voltage Reference Source Select
    411
- DAC Resets
  412
- DAC Clocks
  412
- DAC Interrupts
  412
- CMP Trigger Mode
  412
Chapter 25 12-Bit Digital-To-Analog Converter (DAC)

413
- Introduction
  413
- Features
  413
- Block Diagram
  413
- Memory Map/Register Definition
  414
  - DAC Data Low Register (Dacx_Datnl)
    415
  - DAC Data High Register (Dacx_Datnh)
    415
  - DAC Status Register (Dacx_Sr)
    416
  - DAC Control Register (Dacx_C0)
    417
  - DAC Control Register 1 (Dacx_C1)
    418
  - DAC Control Register 2 (Dacx_C2)
    418
- Functional Description
  419
  - DAC Data Buffer Operation
    419
  - DMA Operation
    421
  - Resets
    421
  - Low-Power Mode Operation
    421
Chapter 26 Voltage Reference (VREFV1)

423
- Introduction
  423
  - Overview
    424
  - Features
    424
  - Modes of Operation
    424
  - VREF Signal Descriptions
    425
- Memory Map and Register Definition
  425
  - VREF Trim Register (VREF_TRM)
    426
  - VREF Status and Control Register (VREF_SC)
    427
- Functional Description
  428
  - Voltage Reference Disabled, SC[VREFEN] = 0
    428
  - Voltage Reference Enabled, SC[VREFEN] = 1
    428
- Internal Voltage Regulator
  430
- Initialization/Application Information
  430
Chapter 27 Multipurpose Clock Generator Lite (Mcg_Lite)

433
- Introduction
  433
  - Features
    433
  - Block Diagram
    434
- Memory Map and Register Definition
  434
- Functional Description
  439
  - Clock Mode Switching
    439
  - LIRC Divider 1
    440
  - LIRC Divider 2
    440
  - Enable LIRC in Stop Mode
    440
  - MCG-Lite in Low-Power Mode
    441
  - HIRC USB Recovery
    441
Chapter 28 Oscillator (OSC)

443
- Chip-Specific OSC Information
  443
  - OSC Modes of Operation with Mcg_Lite and RTC
    443
- Introduction
  443
- Features and Modes
  443
- Block Diagram
  444
- OSC Signal Descriptions
  445
- External Crystal / Resonator Connections
  445
- External Clock Connections
  447
- Memory Map/Register Definitions
  447
  - OSC Memory Map/Register Definition
    448
- Functional Description
  449
  - OSC Module States
    449
  - OSC Module Modes
    451
  - Counter
    453
  - Reference Clock Pin Requirements
    453
- Reset
  453
- Low Power Modes Operation
  454
- Interrupts
  454
- Chip-Specific TPM Information
  455
Chapter 29

455
- TPM Instantiation Information
  455
- Clock Options
  456
- Trigger Options
  457
- Global Timebase
  457
- TPM Interrupts
  457
- Introduction
  458
  - TPM Philosophy
    458
  - Features
    458
  - Modes of Operation
    459
  - Block Diagram
    459
- TPM Signal Descriptions
  460
  - TPM_EXTCLK - TPM External Clock
    460
  - Tpm_Chn - TPM Channel (N) I/O Pin
    461
- Memory Map and Register Definition
  461
  - Status and Control (Tpmx_Sc)
    463
  - Counter (Tpmx_Cnt)
    464
  - Modulo (Tpmx_Mod)
    465
  - Channel (N) Status and Control (Tpmx_Cnsc)
    466
  - Channel (N) Value (Tpmx_Cnv)
    468
  - Capture and Compare Status (Tpmx_Status)
    468
  - Channel Polarity (Tpmx_Pol)
    470
  - Configuration (Tpmx_Conf)
    471
- Functional Description
  474
  - Clock Domains
    474
  - Prescaler
    475
  - Counter
    475
  - Input Capture Mode
    478
  - Output Compare Mode
    479
  - Edge-Aligned PWM (EPWM) Mode
    480
  - Center-Aligned PWM (CPWM) Mode
    482
  - Registers Updated from Write Buffers
    484
  - Dma
    485
  - Output Triggers
    485
  - Reset Overview
    486
  - TPM Interrupts
    486
- Chip-Specific PIT Information
  487
Chapter 30

487
- PIT/DMA Periodic Trigger Assignments
  487
- PIT/ADC Triggers
  487
- PIT/TPM Triggers
  487
- PIT/DAC Triggers
  487
- Introduction
  488
  - Block Diagram
    488
  - Features
    488
- Signal Description
  489
- Memory Map/Register Description
  489
- Functional Description
  494
  - General Operation
    495
  - Interrupts
    496
  - Chained Timers
    496
- Initialization and Application Information
  496
- Example Configuration for Chained Timers
  497
- Example Configuration for the Lifetime Timer
  498
Chapter 31 Low-Power Timer (LPTMR)

501
- Chip-Specific LPTMR Information
  501
- Introduction
  502
  - Features
    502
  - Modes of Operation
    503
- LPTMR Signal Descriptions
  503
  - Detailed Signal Descriptions
    503
- Memory Map and Register Definition
  504
- Functional Description
  508
  - LPTMR Power and Reset
    508
  - LPTMR Clocking
    508
  - LPTMR Prescaler/Glitch Filter
    509
  - LPTMR Compare
    510
  - LPTMR Counter
    510
  - LPTMR Hardware Trigger
    511
  - LPTMR Interrupt
    511
Chapter 32 Real Time Clock (RTC)

513
- Chip-Specific RTC Information
  513
  - RTC Instantiation Information
    513
  - RTC_CLKOUT Options
    513
- Introduction
  513
  - Features
    514
  - Modes of Operation
    514
  - RTC Signal Descriptions
    514
- Register Definition
  514
- Functional Description
  523
  - Power, Clocking, and Reset
    523
  - Time Counter
    524
  - Compensation
    524
  - Time Alarm
    525
  - Update Mode
    526
  - Register Lock
    526
  - Interrupt
    526
Chapter 33 Universal Serial Bus (USB) FS Subsystem

527
- Chip-Specific USBFS Information
  527
  - USB Wakeup
    527
  - USB Power Distribution
    528
  - USB Power Management
    530
- Introduction
  530
  - References
    530
  - Usb
    531
  - USBFS Features
    532
- Functional Description
  532
  - Data Structures
    532
  - On-Chip Transceiver Required External Components
    533
- Programmers Interface
  534
  - Buffer Descriptor Table
    534
  - USB Data Transfers-Receive (Rx) and Transmit (Tx)
    535
  - Addressing BDT Entries
    536
  - Buffer Descriptors (Bds)
    536
  - USB Transaction
    539
- Memory Map/Register Definitions
  541
- Device Mode IRC48 Operation
  561
Chapter 34 USB Voltage Regulator (VREG)

563
- Introduction
  563
  - Overview
    563
  - Features
    564
  - Modes of Operation
    565
- USB Voltage Regulator Module Signal Descriptions
  565
Chapter 35 Serial Peripheral Interface (SPI)

567
- Chip-Specific SPI Information
  567
- Introduction
  567
  - Features
    568
  - Modes of Operation
    569
  - Block Diagrams
    569
- External Signal Description
  572
  - SPSCK - SPI Serial Clock
    573
  - MOSI - Master Data Out, Slave Data in
    573
  - MISO - Master Data In, Slave Data out
    573
  - SS - Slave Select
    573
- Memory Map/Register Definition
  574
  - SPI Status Register (Spix_S)
    574
  - SPI Baud Rate Register (Spix_Br)
    578
  - SPI Control Register 2 (Spix_C2)
    579
  - SPI Control Register 1 (Spix_C1)
    581
  - SPI Match Register Low (Spix_Ml)
    582
  - SPI Match Register High (Spix_Mh)
    583
  - SPI Data Register Low (Spix_Dl)
    583
  - SPI Data Register High (Spix_Dh)
    584
  - SPI Clear Interrupt Register (Spix_Ci)
    585
  - SPI Control Register 3 (Spix_C3)
    586
- Functional Description
  588
  - General
    588
  - Master Mode
    588
  - Slave Mode
    590
  - SPI FIFO Mode
    591
  - SPI Transmission by DMA
    592
  - Data Transmission Length
    594
  - SPI Clock Formats
    595
  - SPI Baud Rate Generation
    598
  - Special Features
    598
  - Error Conditions
    600
  - Low-Power Mode Options
    601
  - Reset
    602
  - Interrupts
    603
- Initialization/Application Information
  605
  - Initialization Sequence
    605
  - Pseudo-Code Example
    606
Chapter 36 Inter-Integrated Circuit (I2C)

611
- Chip-Specific I2C Information
  611
  - I2C Instantiation Information
    611
- Introduction
  611
  - Features
    612
  - Modes of Operation
    612
  - Block Diagram
    613
- I2C Signal Descriptions
  613
- Memory Map/Register Definition
  614
- Functional Description
  627
  - I2C Protocol
    627
  - 10-Bit Address
    632
  - Address Matching
    634
  - System Management Bus Specification
    635
  - Resets
    637
  - Interrupts
    638
  - Programmable Input Glitch Filter
    640
  - Address Matching Wake-Up
    640
  - DMA Support
    641
  - Double Buffering Mode
    642
- Initialization/Application Information
  643
Chapter 37 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)

647
- Chip-Specific LPUART Information
  647
  - LPUART0 and LPUART1 Overview
    647
- Introduction
  647
  - Features
    647
  - Modes of Operation
    648
  - Signal Descriptions
    649
  - Block Diagram
    649
- Register Definition
  651
- Functional Description
  665
  - Baud Rate Generation
    665
  - Transmitter Functional Description
    666
  - Receiver Functional Description
    668
  - Additional LPUART Functions
    673
  - Interrupts and Status Flags
    675
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART)

677
- Chip-Specific UART Information
  677
  - UART2 Overview
    677
- Introduction
  677
  - Features
    677
  - Modes of Operation
    679
- UART Signal Descriptions
  680
  - Detailed Signal Descriptions
    680
- Memory Map and Registers
  680
- Functional Description
  708
  - Transmitter
    708
  - Receiver
    712
  - Baud Rate Generation
    724
  - Data Format (Non ISO-7816)
    726
  - Single-Wire Operation
    729
  - Loop Operation
    729
  - ISO-7816/Smartcard Support
    730
- Reset
  735
- System Level Interrupt Sources
  735
  - RXEDGIF Description
    736
- DMA Operation
  737
- Application Information
  738
- Chip-Specific Flexio Information
  745
Chapter 39

745
- Flexio Instantiation
  745
- Flexio Trigger Options
  745
- Introduction
  746
  - Overview
    746
  - Features
    746
  - Block Diagram
    747
  - Modes of Operation
    747
  - Flexio Signal Descriptions
    748
- Memory Map and Registers
  748
- Functional Description
  767
  - Shifter Operation
    767
  - Timer Operation
    769
  - Pin Operation
    771
- Application Information
  772
  - UART Transmit
    772
  - UART Receive
    773
  - SPI Master
    775
  - SPI Slave
    777
  - I2C Master
    779
  - I2S Master
    781
  - I2S Slave
    782
Chapter 40 Synchronous Audio Interface (SAI)

785
- Chip-Specific I2S Information
  785
  - Instantiation Information
    785
  - I2S Interrupts
    785
  - I2S/SAI Clocking
    785
  - I2S/SAI Operation in Low Power Modes
    787
- Introduction
  788
  - Features
    788
  - Block Diagram
    789
  - Modes of Operation
    789
- External Signals
  790
- Memory Map and Register Definition
  791
- Functional Description
  812
  - SAI Clocking
    812
  - SAI Resets
    814
  - Synchronous Modes
    815
  - Frame Sync Configuration
    815
  - Data FIFO
    816
  - Word Mask Register
    819
  - Interrupts and DMA Requests
    819
- Chip-Specific GPIO Information
  821
  - GPIO Instantiation Information
    821
  - GPIO Accessibility in the Memory Map
    821
- Introduction
  822
  - Features
    822
  - Modes of Operation
    822
  - GPIO Signal Descriptions
    822
Chapter 41 General-Purpose Input/Output (GPIO)

823
- Memory Map and Register Definition
  824
- Functional Description
  828
  - General-Purpose Input
    828
  - General-Purpose Output
    828
Chapter 42

831
Bit Manipulation Engine (BME)

831
- Introduction
  831
  - Overview
    832
  - Features
    832
  - Modes of Operation
    833
- Memory Map and Register Definition
  833
- Functional Description
  833
- Application Information
  848
Chapter 43 Micro Trace Buffer (MTB)

851
- Introduction
  851
  - Overview
    851
  - Features
    854
  - Modes of Operation
    855
- External Signal Description
  855
- Memory Map and Register Definition
  856
  - MTB_RAM Memory Map
    856
  - MTB_DWT Memory Map
    868
  - System ROM Memory Map
    878
Chapter 44

883
Flash Memory Controller (FMC)

883
- Functional Description
  884
Chapter 45 Flash Memory Module (FTFA)

887
- Introduction
  887
  - Features
    887
  - Block Diagram
    888
  - Glossary
    889
- External Signal Description
  890
- Memory Map and Registers
  890
  - Flash Configuration Field Description
    891
  - Program Flash IFR Map
    891
  - Register Descriptions
    892
- Functional Description
  901
  - Flash Protection
    901
  - Interrupts
    902
  - Flash Operation in Low-Power Modes
    903
  - Functional Modes of Operation
    903
  - Flash Reads and Ignored Writes
    903
  - Read While Write (RWW)
    904
  - Flash Program and Erase
    904
  - Flash Command Operations
    904
  - Margin Read Commands
    910
  - Flash Command Description
    911
  - Security
    927
  - Reset Sequence
    929

NXP Semiconductors Categories

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NXP Semiconductors MKL27Z256VLH4 Manuals

NXP Semiconductors MKL27Z256VLH4 Reference Manual (939 pages)

Table of Contents

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3

Core Overview

Chapter 4 Memory Map

Chapter 5

Chapter 6 Reset and Boot

Chapter 7 Power Management

Chapter 8 Security

Chapter 9 Debug

Chapter 10 Pinouts and Packaging

Chapter 11 Port Control and Interrupts (PORT)

Chapter 12 System Integration Module (SIM)

Chapter 13

Chapter 14 System Mode Controller (SMC)

Chapter 15 Power Management Controller (PMC)

Chapter 16 Miscellaneous Control Module (MCM)

Chapter 17 Crossbar Switch Lite (AXBS-Lite)

Chapter 18 Low-Leakage Wakeup Unit (LLWU)

Chapter 19 Peripheral Bridge (AIPS-Lite)

Chapter 20 Direct Memory Access Multiplexer (DMAMUX)

Chapter 21 DMA Controller Module

Chapter 22 Reset Control Module (RCM)

Chapter 23 Analog-To-Digital Converter (ADC)

Chapter 24 Comparator (CMP)

Chapter 25 12-Bit Digital-To-Analog Converter (DAC)

Chapter 26 Voltage Reference (VREFV1)

Chapter 27 Multipurpose Clock Generator Lite (Mcg_Lite)

Chapter 28 Oscillator (OSC)

Chapter 29

Chapter 30

Chapter 31 Low-Power Timer (LPTMR)

Chapter 32 Real Time Clock (RTC)

Chapter 33 Universal Serial Bus (USB) FS Subsystem

Chapter 34 USB Voltage Regulator (VREG)

Chapter 35 Serial Peripheral Interface (SPI)

Chapter 36 Inter-Integrated Circuit (I2C)

Chapter 37 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)

Chapter 38 Universal Asynchronous Receiver/Transmitter(UART)

Chapter 39

Chapter 40 Synchronous Audio Interface (SAI)

Chapter 41 General-Purpose Input/Output (GPIO)

Chapter 42

Bit Manipulation Engine (BME)

Chapter 43 Micro Trace Buffer (MTB)

Chapter 44

Flash Memory Controller (FMC)

Chapter 45 Flash Memory Module (FTFA)

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