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Memory map and register definition
Field
RDR
Receive Data Register
The corresponding RCR3[RCE] bit must be set before accessing the channel's receive data register.
Reads from this register when the receive FIFO is not empty will return the data from the top of the receive
FIFO. Reads from this register when the receive FIFO is empty are ignored.
40.4.14 SAI Receive Mask Register (I2Sx_RMR)
This register is double-buffered and updates:
1. When RCSR[RE] is first set
2. At the end of each frame
This allows the masked words in each frame to change from frame to frame.
Address: 4002_F000h base + E0h offset = 4002_F0E0h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–2
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
RWM
Receive Word Mask
Configures whether the receive word is masked (received data ignored and not written to receive FIFO) for
the corresponding word in the frame.
0
Word N is enabled.
1
Word N is masked.
810
I2Sx_RDRn field descriptions
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
I2Sx_RMR field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
Description
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc.
1
0
RWM
0
0
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