Rtc Time Seconds Register (Rtc_Tsr); Rtc Time Prescaler Register (Rtc_Tpr) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Writing to a register protected by the lock register does not generate a bus error, but the
write will not complete.
Absolute
address
(hex)
4003_D000 RTC Time Seconds Register (RTC_TSR)
4003_D004 RTC Time Prescaler Register (RTC_TPR)
4003_D008 RTC Time Alarm Register (RTC_TAR)
4003_D00C RTC Time Compensation Register (RTC_TCR)
4003_D010 RTC Control Register (RTC_CR)
4003_D014 RTC Status Register (RTC_SR)
4003_D018 RTC Lock Register (RTC_LR)
4003_D01C RTC Interrupt Enable Register (RTC_IER)

32.3.1 RTC Time Seconds Register (RTC_TSR)

Address: 4003_D000h base + 0h offset = 4003_D000h
Bit 31 30 29 28 27 26
R
W
0 0 0 0 0 0
Reset
Field
TSR Time Seconds Register
When the time counter is enabled, the TSR is read only and increments once a second provided SR[TOF]
or SR[TIF] are not set. The time counter will read as zero when SR[TOF] or SR[TIF] are set. When the
time counter is disabled, the TSR can be read or written. Writing to the TSR when the time counter is
disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is supported, but not
recommended because TSR will read as zero when SR[TIF] or SR[TOF] are set (indicating the time is
invalid).

32.3.2 RTC Time Prescaler Register (RTC_TPR)

Address: 4003_D000h base + 4h offset = 4003_D004h
Bit 31 30 29 28 27 26
R
W
0 0 0 0 0 0
Reset
Freescale Semiconductor, Inc.
RTC memory map
Register name
25 24 23 22 21 20 19 18
0 0 0 0 0 0 0 0
RTC_TSR field descriptions
25 24 23 22 21 20 19 18
0
0 0 0 0 0 0 0 0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Width
(in bits)
32
32
32
32
32
32
32
32
17 16 15 14 13 12 11 10
TSR
0 0 0 0 0 0 0 0
Description
17 16 15 14 13 12 11 10
0 0 0 0 0 0 0 0
Chapter 32 Real Time Clock (RTC)
Section/
Access Reset value
R/W 0000_0000h 32.3.1/515
R/W 0000_0000h 32.3.2/515
R/W 0000_0000h 32.3.3/516
R/W 0000_0000h 32.3.4/516
R/W 0000_0000h 32.3.5/518
R/W 0000_0001h 32.3.6/520
R/W 0000_00FFh 32.3.7/521
R/W 0000_0007h 32.3.8/522
9 8 7 6 5 4 3
0 0 0 0 0 0 0
9 8 7 6 5 4 3
TPR
0 0 0 0 0 0 0
page
2 1 0
0 0 0
2 1 0
0 0 0
515