Adc Minus-Side General Calibration Value Register (Adcx_Clm2); Adc Minus-Side General Calibration Value Register (Adcx_Clm1) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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Memory map and register definitions
Field
CLM3
Calibration Value
Calibration Value
23.4.22 ADC Minus-Side General Calibration Value Register
(ADCx_CLM2)
For more information, see CLMD register description.
Address: 4003_B000h base + 64h offset = 4003_B064h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–8
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
CLM2
Calibration Value
Calibration Value
23.4.23 ADC Minus-Side General Calibration Value Register
(ADCx_CLM1)
For more information, see CLMD register description.
Address: 4003_B000h base + 68h offset = 4003_B068h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–7
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
CLM1
Calibration Value
Calibration Value
362
ADCx_CLM3 field descriptions (continued)
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
ADCx_CLM2 field descriptions
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
ADCx_CLM1 field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
Description
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
Description
9
8
7
6
5
4
3
2
CLM2
0
0
1
0
0
0
0
0
9
8
7
6
5
4
3
2
CLM1
0
0
0
1
0
0
0
0
Freescale Semiconductor, Inc.
1
0
0
0
1
0
0
0

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