Inter-Integrated Circuit (I2C); Chip-Specific I2C Information; I2C Instantiation Information; Introduction - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Inter-Integrated Circuit (I2C)

This device has two IIC modules. I2Cx are clocked by the system clock so they can

support standard IIC communication rates of 100 kbit/s in VLPR mode.

When the package pins associated with IIC have their mux select configured for IIC

operation, the pins (SCL and SDA) are driven either by true open drain or in a pseudo

open drain configuration. However, only pseudo open drain configuration is for KLx3

The digital glitch filter implemented in the IICx module, controlled by the

I2Cx_FLT[FLT] registers, is clocked from the core/system clock and thus has filter

granularity in core/system clock cycle counts.

For I2C instance 0, I2C0_C2[HDRS] is available. For I2C

instance 1, I2C1_C2[HDRS] is not available.

The inter-integrated circuit (I

communication between a number of devices.

The interface is designed to operate up to at least 400 kbit/s with maximum bus loading

and timing. The I2C device is capable of operating at higher baud rates, up to a maximum

of clock/20, with reduced bus loading. The maximum communication length and the

Freescale Semiconductor, Inc.

C, I2C, or IIC) module provides a method of

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016