Uart Control Register 2 (Uartx_C2) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Field
Determines whether the UART generates and checks for even parity or odd parity. With even parity, an
even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd
number of 1s clears the parity bit and an even number of 1s sets the parity bit. This field must be cleared
when C7816[ISO_7816E] is set/enabled.
0 Even parity.
1 Odd parity.

38.4.4 UART Control Register 2 (UARTx_C2)

This register can be read or written at any time.
Address: 4006_C000h base + 3h offset = 4006_C003h
Bit 7
Read
TIE
Write
Reset 0
Field
7 Transmitter Interrupt or DMA Transfer Enable.
TIE
Enables S1[TDRE] to generate interrupt requests or DMA transfer requests, based on the state of
C5[TDMAS].
NOTE: If C2[TIE] and C5[TDMAS] are both set, then TCIE must be cleared, and D[D] must not be written
0 TDRE interrupt and DMA transfer requests disabled.
1 TDRE interrupt or DMA transfer requests enabled.
6 Transmission Complete Interrupt Enable
TCIE
Enables the transmission complete flag, S1[TC], to generate interrupt requests .
0 TC interrupt requests disabled.
1
TC interrupt requests enabled.
5 Receiver Full Interrupt or DMA Transfer Enable
RIE
Enables S1[RDRF] to generate interrupt requests or DMA transfer requests, based on the state of
C5[RDMAS].
0 RDRF interrupt and DMA transfer requests disabled.
1 RDRF interrupt or DMA transfer requests enabled.
4 Idle Line Interrupt Enable
ILIE
Enables the idle line flag, S1[IDLE], to generate interrupt requests
Freescale Semiconductor, Inc.
UARTx_C1 field descriptions (continued)
6 5
TCIE RIE
0 0
UARTx_C2 field descriptions
unless servicing a DMA request.
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART)
Description
4 3
ILIE TE
0 0
Description
2 1
RE RWU SBK
0 0
0
0
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