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40.4.15 SAI MCLK Control Register (I2Sx_MCR)
The MCLK Control Register (MCR) controls the clock source and direction of the audio
master clock.
Address: 4002_F000h base + 100h offset = 4002_F100h
Bit
31
30
29
DUF
R
MOE
W
Reset
0
0
0
15
14
13
Bit
R
W
Reset
0
0
0
Field
31
Divider Update Flag
DUF
Provides the status of on-the-fly updates to the MCLK divider ratio.
0
MCLK divider ratio is not being updated currently.
1
MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while
this flag remains set.
30
MCLK Output Enable
MOE
Enables the MCLK divider and configures the MCLK signal pin as an output. When software clears this
field, it remains set until the MCLK divider is fully disabled.
0
MCLK signal pin is configured as an input that bypasses the MCLK divider.
1
MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.
29–26
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
25–24
MCLK Input Clock Select
MICS
Selects the clock input to the MCLK divider. This field cannot be changed while the MCLK divider is
enabled. See the chip-specific information for the connections to these inputs.
00
MCLK divider input clock 0 is selected.
01
MCLK divider input clock 1 is selected.
10
MCLK divider input clock 2 is selected.
11
MCLK divider input clock 3 is selected.
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Freescale Semiconductor, Inc.
28
27
26
25
0
MICS
0
0
0
0
12
11
10
9
0
0
0
0
I2Sx_MCR field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 40 Synchronous Audio Interface (SAI)
24
23
22
21
0
0
0
0
8
7
6
5
0
0
0
0
0
Description
20
19
18
17
0
0
0
0
0
4
3
2
1
0
0
0
0
16
0
0
0
811
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