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Flash memory
4.2.1 Flash memory map
The flash memory and the flash registers are located at different base addresses as shown
in the figure found here.
The base address for each is specified in
System memory
map.
Flash memory base address
Registers
Flash base address
Flash configuration field
Flash
Figure 4-1. Flash memory map
The on-chip flash memory is implemented in a portion of the allocated Flash range to
form a contiguous block in the memory map beginning at address 0x0000_0000. See
Flash memory
for details of supported ranges.
Access to the flash memory ranges outside the amount of flash on the device causes the
bus cycle to be terminated with an error followed by the appropriate response in the
requesting bus master.
4.2.2 Flash security
For information on how flash security is implemented on this device, see Security.
4.2.3 Flash modes
The flash memory chapter defines two modes of operation: NVM normal and NVM
special modes. On this device, the flash memory only operates in NVM normal mode. All
references to NVM special mode must be ignored.
4.2.4 Erase all flash contents
In addition to software, the entire flash memory may be erased external to the flash
memory via the SW-DP debug port by setting MDM-AP CONTROL[0]. MDM-AP
STATUS[0] is set to indicate the mass erase command has been accepted. MDM-AP
STATUS[0] is cleared when the mass erase completes.
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
56
Freescale Semiconductor, Inc.
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