Introduction; Block Diagram; Features - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Introduction

30.1.4 PIT/DAC triggers
PIT Channel 0 is configured as the DAC hardware trigger source. For more details, see
the DAC chapter.
30.2 Introduction
The PIT module is an array of timers that can be used to raise interrupts and trigger DMA
channels.

30.2.1 Block diagram

The following figure shows the block diagram of the PIT module.
Peripheral bus
Interrupts
Triggers
Peripheral
bus clock
See the chip-specific PIT information for the number of PIT
channels used in this MCU.
488
PIT
PIT
registers
Figure 30-1. Block diagram of the PIT
NOTE
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
load_value
Timer 1
Timer n
Freescale Semiconductor, Inc.