Block Diagram; Memory Map And Register Definition - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

27.1.2 Block diagram

The block diagram of MCG_Lite is as follows.

27.2 Memory map and register definition

The MCG_Lite module contains several fields for selecting the clock source and the

dividers for various module clocks.

The MCG_Lite registers can be written only in supervisor

mode. Write accesses in user mode are blocked and will result

in a bus error.

HGO0 / RANGE0

Figure 27-1. MCG_Lite block diagram

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Clock Switcher

CLKST OSCINIT

Freescale Semiconductor, Inc.

LIRC_DIV1_CLK