Table of Contents
Advertisement
Register definition
Field
31–16
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
TPR
Time Prescaler Register
When the time counter is enabled, the TPR is read only and increments every 32.768 kHz clock cycle. The
time counter will read as zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the
TPR can be read or written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
to a logic zero.
32.3.3 RTC Time Alarm Register (RTC_TAR)
Address: 4003_D000h base + 8h offset = 4003_D008h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
TAR
Time Alarm Register
When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] equals the TSR[TSR] and
the TSR[TSR] increments. Writing to the TAR clears the SR[TAF].
32.3.4 RTC Time Compensation Register (RTC_TCR)
Address: 4003_D000h base + Ch offset = 4003_D00Ch
Bit
31
30
29
28
27
26
CIC
R
W
0
0
0
0
0
0
Reset
Field
31–24
Compensation Interval Counter
CIC
Current value of the compensation interval counter. If the compensation interval counter equals zero then
it is loaded with the contents of the CIR. If the CIC does not equal zero then it is decremented once a
second.
23–16
Time Compensation Value
TCV
516
RTC_TPR field descriptions
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
RTC_TAR field descriptions
25
24
23
22
21
20
19
18
TCV
0
0
0
0
0
0
0
0
RTC_TCR field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
17
16
15
14
13
12
11
10
TAR
0
0
0
0
0
0
0
0
Description
17
16
15
14
13
12
11
10
CIR
0
0
0
0
0
0
0
0
Description
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
TCR
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc.
1
0
0
0
1
0
0
0
Advertisement
Table of Contents
