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Name
SAI_RX_DATA
SAI_MCLK
40.4 Memory map and register definition
A read or write access to an address from offset 0x108 and above will result in a bus
error.
Absolute
address
(hex)
4002_F000
SAI Transmit Control Register (I2S0_TCSR)
4002_F008
SAI Transmit Configuration 2 Register (I2S0_TCR2)
4002_F00C SAI Transmit Configuration 3 Register (I2S0_TCR3)
4002_F010
SAI Transmit Configuration 4 Register (I2S0_TCR4)
4002_F014
SAI Transmit Configuration 5 Register (I2S0_TCR5)
4002_F020
SAI Transmit Data Register (I2S0_TDR0)
4002_F060
SAI Transmit Mask Register (I2S0_TMR)
4002_F080
SAI Receive Control Register (I2S0_RCSR)
4002_F088
SAI Receive Configuration 2 Register (I2S0_RCR2)
4002_F08C SAI Receive Configuration 3 Register (I2S0_RCR3)
4002_F090
SAI Receive Configuration 4 Register (I2S0_RCR4)
4002_F094
SAI Receive Configuration 5 Register (I2S0_RCR5)
4002_F0A0 SAI Receive Data Register (I2S0_RDR0)
4002_F0E0 SAI Receive Mask Register (I2S0_RMR)
4002_F100
SAI MCLK Control Register (I2S0_MCR)
Freescale Semiconductor, Inc.
externally generated and an output generated
synchronously by the bit clock when internally
generated.
Receive Data. The receive data is sampled
synchronously by the bit clock.
Audio Master Clock. The master clock is an input
when externally generated and an output when
internally generated.
I2S memory map
Register name
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 40 Synchronous Audio Interface (SAI)
Function
Width
Access
Reset value
(in bits)
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
W
32
(always
0000_0000h
reads 0)
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
I/O
I
I/O
Section/
page
40.4.1/792
40.4.2/795
40.4.3/796
40.4.4/797
40.4.5/799
40.4.6/800
40.4.7/800
40.4.8/801
40.4.9/804
40.4.10/
806
40.4.11/
807
40.4.12/
809
40.4.13/
809
40.4.14/
810
40.4.15/
811
791
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