Cmp Control Register 1 (Cmpx_Cr1) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map/register definitions
Field
HYSTCTR Comparator hard block hysteresis control
Defines the programmable hysteresis level. The hysteresis values associated with each level are device-
specific. See the Data Sheet of the device for the exact values.
00 Level 0
01 Level 1
10 Level 2
11 Level 3

24.3.2 CMP Control Register 1 (CMPx_CR1)

Address: 4007_3000h base + 1h offset = 4007_3001h
Bit 7
Read
SE
Write
Reset
0
Field
7 Sample Enable
SE
SE must be clear to 0 and usage of sample operation is limited to a divided version of the bus clock.
0 Sampling mode is not selected.
1 Sampling mode is selected.
6 Windowing Enable
WE
The CMP does not support window compare function and a 0 must always be written to WE.
0 Windowing mode is not selected.
1 Windowing mode is selected.
5 Trigger Mode Enable
TRIGM
CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to 1. In addition, the
CMP should be enabled. If the DAC is to be used as a reference to the CMP, it should also be enabled.
CMP Trigger mode depends on an external timer resource to periodically enable the CMP and 6-bit DAC
in order to generate a triggered compare.
Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resource
trigger is received.
See the chip configuration for details about the external timer resource.
0 Trigger mode is disabled.
1 Trigger mode is enabled.
4 Power Mode Select
PMODE
398
CMPx_CR0 field descriptions (continued)
6 5
WE TRIGM PMODE
0 0
CMPx_CR1 field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
4 3
INV COS
0 0
Description
2 1
OPE EN
0 0
Freescale Semiconductor, Inc.
0
0