Pit Module Control Register (Pit_Mcr) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map/register description

30.4.1 PIT Module Control Register (PIT_MCR)

This register enables or disables the PIT timer clocks and controls the timers when the
PIT enters the Debug mode.
Access: User read/write
Address: 4003_7000h base + 0h offset = 4003_7000h
Bit 31 30 29
R
W
Reset 0 0 0
Bit 15 14 13
R
W
Reset
0 0 0
Field
31–3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
2 This field is reserved.
Reserved
1 Module Disable - (PIT section)
MDIS
Disables the standard timers. This field must be enabled before any other setup is done.
0 Clock for standard PIT timers is enabled.
1 Clock for standard PIT timers is disabled.
490
28 27 26 25
0 0 0 0
12 11 10 9
0
0 0 0 0
PIT_MCR field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
24 23 22 21
0
0 0 0 0
8 7 6 5
0 0 0 0
Description
20 19 18 17
0 0 0 0
4 3 2 1
MDIS
0 0 0 1
Freescale Semiconductor, Inc.
16
0
0
FRZ
0