Dma Control Register (Dma_Dcrn) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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Set when all DMA controller transactions complete as determined by transfer count, or based on error

conditions. When BCR reaches 0, DONE is set when the final transfer completes successfully. DONE can

also be used to abort a transfer by resetting the status bits. When a transfer completes, software must

clear DONE before reprogramming the DMA.

DMA transfer is not yet complete. Writing a 0 has no effect.

DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an

interrupt service routine to clear the DMA interrupt and error bits.

This field contains the number of bytes yet to be transferred for a given block.

Restriction: BCR must be written with a value equal to or less than 0F_FFFFh. After being written with a

21.3.4 DMA Control Register (DMA_DCRn)

Address: 4000_8000h base + 10Ch offset + (16d × i), where i=0d to 3d

Enable Interrupt on Completion of Transfer

Freescale Semiconductor, Inc.

DMA_DSR_BCRn field descriptions (continued)

value in this range, bits 23-20 of BCR read back as 0000b. A write to BCR of a value

greater than 0F_FFFFh causes a configuration error when the channel starts to execute.

After being written with a value in this range, bits 23-20 of BCR read back as 0001b.

DMA_DCRn field descriptions

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KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 21 DMA Controller Module