Features - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Introduction
The SPI runs at a baud rate up to the SPI module clock divided by two in master mode
and up to the SPI module clock divided by four in slave mode. Software can poll the
status flags, or SPI operation can be interrupt driven.
For the actual maximum SPI baud rate, refer to the Chip
Configuration details and to the device's Data Sheet.
The SPI also supports a data length of 8 or 16 bits and includes a hardware match feature
for the receive data buffer.
The SPI includes an internal DMA interface to support continuous SPI transmission
through an on-chip DMA controller instead of through the CPU. This feature decreases
CPU loading, allowing CPU time to be used for other work.

35.2.1 Features

The SPI includes these distinctive features:
• Master mode or slave mode operation
• Full-duplex or single-wire bidirectional mode
• Programmable transmit bit rate
• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed/large amounts of data transfers
• Support transmission of both Transmit and Receive by DMA
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NOTE
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.