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23.4.16 ADC Plus-Side General Calibration Value Register
(ADCx_CLP1)
For more information, see CLPD register description.
Address: 4003_B000h base + 48h offset = 4003_B048h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–7
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
CLP1
Calibration Value
Calibration Value
23.4.17 ADC Plus-Side General Calibration Value Register
(ADCx_CLP0)
For more information, see CLPD register description.
Address: 4003_B000h base + 4Ch offset = 4003_B04Ch
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–6
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
CLP0
Calibration Value
Calibration Value
Freescale Semiconductor, Inc.
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
ADCx_CLP1 field descriptions
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
ADCx_CLP0 field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 23 Analog-to-Digital Converter (ADC)
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
Description
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
Description
9
8
7
6
5
4
3
2
CLP1
0
0
0
1
0
0
0
0
9
8
7
6
5
4
3
2
CLP0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
359
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