Features; Modes Of Operation - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Introduction

number of devices that can be connected are limited by a maximum bus capacitance of

400 pF. The I2C module also complies with the System Management Bus (SMBus)

Specification, version 2.

36.2.1 Features

The I2C module has the following features:

• Compatible with The I

• Multimaster operation

• Software programmable for one of 64 different serial clock frequencies

• Software-selectable acknowledge bit

• Interrupt-driven byte-by-byte data transfer

• Arbitration-lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• START and STOP signal generation and detection

• Repeated START signal generation and detection

• Acknowledge bit generation and detection

• Bus busy detection

• General call recognition

• 10-bit address extension

• Support for System Management Bus (SMBus) Specification, version 2

• Programmable input glitch filter

• Low power mode wakeup on slave address match

• Range slave address support

• DMA support

• Double buffering support to achieve higher baud rate

The I2C module's operation in various low power modes is as follows:

• Run mode: This is the basic mode of operation. To conserve power in this mode,

disable the module.

• Wait mode: The module continues to operate when the core is in Wait mode and can

provide a wakeup interrupt.

• Stop mode: The module is inactive in Stop mode for reduced power consumption,

except that address matching is enabled in Stop mode. The STOP instruction does

not affect the I2C module's register states.

C-Bus Specification

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Freescale Semiconductor, Inc.