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Memory Map and Register Definition
Field
2
Channel 2 Flag
CH2F
See the register description.
0
No channel event has occurred.
1
A channel event has occurred.
1
Channel 1 Flag
CH1F
See the register description.
0
No channel event has occurred.
1
A channel event has occurred.
0
Channel 0 Flag
CH0F
See the register description.
0
No channel event has occurred.
1
A channel event has occurred.
29.4.7 Channel Polarity (TPMx_POL)
This register defines the input and output polarity of each of the channels.
Address: Base address + 70h offset
Bit
31
30
29
R
W
Reset
0
0
0
Bit
15
14
13
R
W
Reset
0
0
0
Field
31–6
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
5
Channel 5 Polarity
POL5
0
The channel polarity is active high.
1
The channel polarity is active low.
4
Channel 4 Polarity
POL4
0
The channel polarity is active high
1
The channel polarity is active low.
470
TPMx_STATUS field descriptions (continued)
28
27
26
25
0
0
0
0
12
11
10
9
0
0
0
0
0
TPMx_POL field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
24
23
22
21
0
0
0
0
0
8
7
6
5
POL5 POL4 POL3 POL2 POL1 POL0
0
0
0
0
Description
20
19
18
17
0
0
0
0
4
3
2
1
0
0
0
0
Freescale Semiconductor, Inc.
16
0
0
0
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