Vref Signal Descriptions; Memory Map And Register Definition - NXP Semiconductors MKL27Z128VFM4 Reference Manual

power modes it may be desirable to disable the VREF regulator to minimize current
consumption. Note however that the accuracy of the output voltage will be reduced (by as
much as several mVs) when the VREF regulator is not used.
The assignment of module modes to core modes is chip-
specific. For module-to-core mode assignments, see the chapter
that describes how modules are configured.

26.1.4 VREF Signal Descriptions

The following table shows the Voltage Reference signals properties.
Signal Description
VREF_OUT Internally-generated Voltage Reference output
When the VREF output buffer is disabled, the status of the
VREF_OUT signal is high-impedence.
26.2

Memory Map and Register Definition

Absolute
address
(hex)
4007_4000 VREF Trim Register (VREF_TRM)
4007_4001 VREF Status and Control Register (VREF_SC)
Freescale Semiconductor, Inc.
NOTE
Table 26-1. VREF Signal Descriptions
NOTE
VREF memory map
Register name
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 26 Voltage Reference (VREFV1)
Width
Access Reset value
(in bits)
8 R/W See section
8 R/W 00h
I/O
O
Section/
page
26.2.1/426
26.2.2/427
425