Functional Description; Transfer Requests (Cycle-Steal And Continuous Modes) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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DMA Channel 2

DMA Channel 3

Link Channel 2

Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the same as

the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set).

DMA Channel 0

DMA Channel 1

DMA Channel 2

DMA Channel 3

21.4 Functional Description

In the following discussion, the term DMA request implies that DCRn[START] is set, or

DCRn[ERQ] is set and then followed by assertion of the properly selected DMA

peripheral request. DCRn[START] is cleared when the channel is activated.

Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE] and

DCRn[DSIZE] are consistent with the source and destination addresses. If they are not

consistent, the configuration error bit, DSRn[CE], is set. If misalignment is detected, no

transfer occurs, DSRn[CE] is set, and, depending on the DCR configuration, an interrupt

event may be issued. If the auto-align bit, DCRn[AA], is set, error checking is performed

on the appropriate registers.

A read/write transfer sequence reads data from the source address and writes it to the

destination address. The number of bytes transferred is the largest of the sizes specified

by DCRn[SSIZE] and DCRn[DSIZE] in the DMA Control Registers (DCRn).

Source and destination address registers (SARn and DARn) can be programmed in the

DCRn to increment at the completion of a successful transfer.

The DMA channel supports software-initiated or peripheral-initiated requests. A request

is issued by setting DCRn[START] or when the selected peripheral request asserts and

DCRn[ERQ] is set. Setting DCRn[ERQ] enables recognition of the peripheral DMA

requests. Selecting between cycle-steal and continuous modes minimizes bus usage for

either type of request.

Freescale Semiconductor, Inc.

DMA_DCRn field descriptions (continued)

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 21 DMA Controller Module