Table of Contents
Advertisement
• Temperature sensor
• Hardware average function
• Selectable voltage reference: external or alternate
• Self-Calibration mode
23.2.2 Block diagram
The following figure is the ADC module block diagram.
ADHWTSA
ADHWTSn
ADHWT
Compare true
1
Interrupt
MCU STOP
DADP0
DADP3
AD4
AD23
TempP
DADM0
DADM3
TempM
V
REFH
V
ALTH
V
REFL
V
ALTL
Freescale Semiconductor, Inc.
Conversion
trigger
control
ADTRG
Control sequencer
ADVINP
ADVINM
SAR converter
Offset subtractor
Averager
Formatting
D
transfer
Compare
logic
CV1
CV2
CV1:CV2
Figure 23-1. ADC block diagram
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 23 Analog-to-Digital Converter (ADC)
SC1A
SC1n
Control Registers
(SC2, CFG1, CFG2)
ADACKEN
ADCK
Clock
divide
PG, MG
CLPx
CLMx
OFS
ADCOFS
CAL
AVGE, AVGS
MODE
RA
Rn
ACFE
ACFGT, ACREN
Compare true
1
Async
Clock Gen
ADACK
Bus clock
2
ALTCLK
PG, MG
CLPx
CLMx
Calibration
CALF
SC3
CFG1,2
SC2
339
Advertisement
Table of Contents
