Llwu Pin Enable 3 Register (Llwu_Pe3) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map/register definition
Field
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
5–4 Wakeup Pin Enable For LLWU_P6
WUPE6
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
3–2 Wakeup Pin Enable For LLWU_P5
WUPE5
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
WUPE4 Wakeup Pin Enable For LLWU_P4
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection

18.4.3 LLWU Pin Enable 3 register (LLWU_PE3)

LLWU_PE3 contains the field to enable and select the edge detect type for the external
wakeup input pins LLWU_P11–LLWU_P8.
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the
Introduction
Address: 4007_C000h base + 2h offset = 4007_C002h
Bit 7
Read
WUPE11
Write
Reset 0
270
LLWU_PE2 field descriptions (continued)
NOTE
details for more information.
6 5
WUPE10
0 0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
4 3
WUPE9
0 0
2 1
WUPE8
0 0
Freescale Semiconductor, Inc.
0
0