Serial Peripheral Interface (Spi); Chip-Specific Spi Information; Introduction - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Serial Peripheral Interface (SPI)

This device contains two SPI modules that support 16-bit data length. SPI1 includes a 4-

deep FIFO, SPI0 does not include FIFO. SPI0 is clocked on the bus clock. SPI1 is

clocked from the system clock. SPI1 is therefore disabled in "Partial Stop Mode". The

SPI supports DMA request and can operate in VLPS mode. When the SPI is operating in

VLPS mode, it operates as a slave. SPI can wake the MCU from VLPS mode upon

reception of SPI data in slave mode. SPI0 operates at maximum configurable speed —

12MHz in Master Mode (Bus/2). SPI1 operates at maximum configurable speed —

24MHz in Master Mode (System clock/2).

The following registers are not available in this device:

Absolute address

SPI0 has no SPI0_CI and SPI0_C3 and relative register bit in

The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial

communication between the MCU and peripheral devices. These peripheral devices can

include other microcontrollers, analog-to-digital converters, shift registers, sensors, and

memories, among others.

Freescale Semiconductor, Inc.

Table 35-1. SPI register

SPI clear interrupt register (SPI0_CI)

SPI control register 3 (SPI0_C3)

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016