Llwu Signal Descriptions; Memory Map/Register Definition - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

18.3 LLWU signal descriptions

The signal properties of LLWU are shown in the table found here.

The external wakeup input pins can be enabled to detect either rising-edge, falling-edge,

or on any change.

Wakeup inputs (n = 0-15 )

The LLWU includes the following registers:

• Wake-up source enable registers

• Enable external pin input sources

• Enable internal peripheral interrupt sources

• Wake-up flag registers

• Indication of wakeup source that caused exit from a low-leakage power mode

includes external pin or internal module interrupt

• Wake-up pin filter enable registers

The LLWU registers can be written only in supervisor mode.

Write accesses in user mode are blocked and will result in a bus

All LLWU registers are reset by Chip Reset not VLLS and by

reset types that trigger Chip Reset not VLLS. Each register's

displayed reset value represents this subset of reset types.

LLWU registers are unaffected by reset types that do not trigger

Chip Reset not VLLS. For more information about the types of

reset on this chip, refer to the

Freescale Semiconductor, Inc.

Table 18-2. LLWU signal descriptions

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 18 Low-Leakage Wakeup Unit (LLWU)

Introduction