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Field
When set, and the frame sync is generated internally, a frame sync is only generated when the FIFO
warning flag is clear.
0
Internal frame sync is generated continuously.
1
Internal frame sync is generated when the FIFO warning flag is clear.
1
Frame Sync Polarity
FSP
Configures the polarity of the frame sync.
0
Frame sync is active high.
1
Frame sync is active low.
0
Frame Sync Direction
FSD
Configures the direction of the frame sync.
0
Frame sync is generated externally in Slave mode.
1
Frame sync is generated internally in Master mode.
40.4.5 SAI Transmit Configuration 5 Register (I2Sx_TCR5)
This register must not be altered when TCSR[TE] is set.
Address: 4002_F000h base + 14h offset = 4002_F014h
Bit
31
30
29
28
27
26
0
R
WNW
W
0
0
0
0
0
0
Reset
Field
31–29
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
28–24
Word N Width
WNW
Configures the number of bits in each word, for each word except the first in the frame. The value written
must be one less than the number of bits per word. Word width of less than 8 bits is not supported.
23–21
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
20–16
Word 0 Width
W0W
Configures the number of bits in the first word in each frame. The value written must be one less than the
number of bits in the first word. Word width of less than 8 bits is not supported if there is only one word per
frame.
15–13
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
Freescale Semiconductor, Inc.
I2Sx_TCR4 field descriptions (continued)
25
24
23
22
21
20
19
18
0
W0W
0
0
0
0
0
0
0
0
I2Sx_TCR5 field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 40 Synchronous Audio Interface (SAI)
Description
17
16
15
14
13
12
11
10
0
FBT
0
0
0
0
0
0
0
0
Description
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
1
0
0
0
799
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