Cmp External References; Cmp Trigger Mode - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Chip-specific CMP information

24.1.2 CMP input connections

The following table shows the fixed internal connections to the CMP0.

1. This is the PMC bandgap 1V reference voltage. Prior to using as CMP input, ensure that you enable the bandgap buffer by

setting PMC_REGSC[BGBE]. See the device data sheet for the bandgap voltage (V

24.1.3 CMP external references

The 6-bit DAC sub-block supports selection of two references. For this device, the

references are connected as follows:

• VREF_OUT–V

same reference at the same time is negatively impacted.

The CMP and 6-bit DAC sub-block supports trigger mode operation when

CMP_CR1[TRIGM] is set. When trigger mode is enabled, the trigger event will initiate a

compare sequence that must first enable the CMP and DAC prior to performing a CMP

operation and capturing the output. In this device, control for this two-staged sequencing

is provided from the LPTMR. The LPTMR triggering output is always enabled when the

LPTMR is enabled. The first signal is supplied to enable the CMP and DAC and is

asserted at the same time as the TCF flag is set. The delay to the second signal that

triggers the CMP to capture the result of the compare operation is dependent on the

LPTMR configuration.

Table 24-1. CMP input connections

input. When using VREF_OUT, any ADC conversion using this

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

12-bit DAC0 reference/ CMP0_IN4

6-bit DAC0 reference

) specification.

Freescale Semiconductor, Inc.