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Memory map and register definition
40.4.10 SAI Receive Configuration 3 Register (I2Sx_RCR3)
Address: 4002_F000h base + 8Ch offset = 4002_F08Ch
Bit
31
30
29
R
W
Reset
0
0
0
15
14
13
Bit
R
W
Reset
0
0
0
Field
31–24
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
23–17
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
16
Receive Channel Enable
RCE
Enables the corresponding data channel for receive operation. A channel must be enabled before its FIFO
is accessed. Changing this field will take effect immediately for generating the FIFO request and warning
flags, but at the end of each frame for receive operation.
0
Receive data channel N is disabled.
1
Receive data channel N is enabled.
15–1
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
0
Word Flag Configuration
WDFL
Configures which word the start of word flag is set. The value written should be one less than the word
number (for example, write zero to configure for the first word in the frame). When configured to a value
greater than the Frame Size field, then the start of word flag is never set.
806
28
27
26
25
0
0
0
0
0
12
11
10
9
0
0
0
0
I2Sx_RCR3 field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
24
23
22
21
0
0
0
0
8
7
6
5
0
0
0
0
0
Description
20
19
18
17
0
0
0
0
0
4
3
2
1
0
0
0
0
Freescale Semiconductor, Inc.
16
RCE
0
0
0
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